JPH06261224A - Pll circuit - Google Patents

Abstract

PURPOSE:To obtain a PLL circuit which is capable of outputting a clock signal phase looked with an input signal within prescribed time by changing a frequency division ratio based on preliminarily stored data according to the phase difference of the input signal and a feedback signal. CONSTITUTION:Phase comparators 1 and 4 detect the phase difference between an input signal and a feedback signal 12, respectively, and output the signals according to the phase difference. The output of the phase comparator 1 is outputted to a counter 7 via an LPF 2 and a VCO 3. An A/D conversion is performed for the output of a phase device 2, the data which is preliminarily stored in a ROM table 6 is taken out according to phase differences and the data is supplied to the counter 7. The counter 7 changes a frequency division ratio according to the data supplied from the ROM 6 and performs the feedback of the feedback signal 12 to the comparators 1 and 4 after a frequency division is performed for a clock signal 11 based on the frequency division ratio. Thus, a clock signal synchronized with the input signal within prescribed time is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit for properly changing the frequency division ratio to match the phase of a feedback signal with a reference signal.

[0002]

2. Description of the Related Art In a clear vision (EDTV) or the like, for example, a PLL circuit (block diagram) shown in FIG. 4 is used in order to obtain a clock signal which is phase-synchronized with a horizontal synchronizing signal of a broadcast color television signal. Reference numeral 31 is a horizontal synchronizing signal 4 of a broadcast color television signal input as a reference signal.
0 and the feedback signal (horizontal synchronizing signal) 42 obtained by dividing the clock signal 41 oscillated and output by the VCO 34 by the counter 37, and generating a signal corresponding to the phase difference between the two signals. Is. 32 is the phase comparator 3
A low-pass filter (LPF) that receives a signal corresponding to the phase difference from 1 and generates a DC voltage based on the signal. Three
A voltage controlled oscillator (VCO) circuit 4 controls the oscillation frequency and phase based on the DC voltage to generate and output a desired clock signal 41. 37 is the clock signal 4
It is a counter (frequency divider) that divides 1 by a predetermined ratio to generate a feedback signal 42. However, the conventional PLL described above
In the circuit, since the division ratio of the counter 37 is a fixed value,
Depending on the timing of turning on the power, etc.
Due to the slow convergence speed determined by the overall characteristics of the VCO 34 connected in cascade with 32, it was not possible to generate a stable clock signal 41 phase-locked to the horizontal sync signal 40 within the required convergence time.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems. When an input (reference) signal is supplied, a clock signal phase-synchronized with the input signal is output within a predetermined time. It is an object of the present invention to provide a PLL circuit that can be used.

[0004]

In order to achieve the above object, first phase difference detecting means for detecting a phase difference between input signals and outputting a signal corresponding to the phase difference, and the phase difference detecting means. A low-pass filter for inputting a signal output from the means, converting the signal to a direct-current voltage and outputting the voltage, and a voltage-controlled oscillating means for connecting the low-pass filter in cascade and generating a predetermined signal controlled by the direct-current voltage and outputting the signal. And a frequency dividing means for dividing the output signal of the voltage controlled oscillating means and for feedback connection to the phase difference detecting means, a signal to be connected and input in parallel with the first phase difference detecting means. Second phase difference detecting means for detecting a phase difference between the two and outputting a signal corresponding to the phase difference; and means for inputting a signal output by the second phase difference detecting means, converting the signal into digital data, and outputting the digital data. ,Input Storage means for outputting a predetermined data stored according to the digital data, and a frequency dividing means for varying the divider ratio according to data supplied from said storage means.

[0005]

With the above-described structure, a predetermined value is stored in the storage means by the quantized digital data based on the phase difference detected by the second phase difference detection means in units of the cycle of the output signal of the voltage controlled oscillation means. Data is taken out, and the data is supplied to the frequency dividing means to change the frequency division ratio so that the phase difference between the generated feedback signal and the reference signal is calculated as a half cycle of the output signal of the voltage controlled oscillation means. Decrease within the period.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
It is an example block diagram of a circuit. Reference numeral 1 is a first phase comparator which detects a phase difference between the input signal 10 and the feedback signal 12 and outputs a signal corresponding to the phase difference. Reference numeral 2 is a low-pass filter that inputs a signal corresponding to the phase difference, converts the signal into a DC voltage, and outputs the DC voltage. Reference numeral 3 denotes a voltage-controlled oscillator that is connected in cascade to the low-pass filter 2 and that is controlled by a DC voltage supplied by the low-pass filter 2 to generate a predetermined clock signal 11. Reference numeral 4 is a second phase comparator connected in parallel with the first phase comparator 1 to detect a phase difference between input signals and output a signal corresponding to the phase difference. 5 is
The digital conversion unit receives a signal output from the second phase comparator, converts the signal into digital data with the cycle of the clock signal 11 as a minimum unit, and outputs the digital data. A ROM table 6 outputs predetermined stored preset data 13 corresponding to the input digital data. 7 is
The frequency division ratio is changed according to the data supplied from the ROM table 6, and the clock signal 11 is frequency-divided based on the frequency division ratio, and then the output (feedback) signal 12 is supplied to the first phase comparator. It is a counter that feeds back to the first and second phase comparators 4.

The operation of the PLL circuit according to the present invention will be described. FIG. 2 is a diagram showing the phase difference of the comparison (feedback) signal with respect to the input (reference) signal in the PLL circuit according to the present invention. (A) is a case where the comparison signal has a delayed phase difference, and (b) is a case where the comparison signal has a leading phase difference. In the figure (a), the comparison signal 12 is compared with the input signal 10 and the cycle 21 of the clock signal is used as a unit.
This indicates that there is a delay phase difference 22 of about 5 cycles.
In the figure (b), the comparison signal 12 is compared with the input signal 10,
It indicates that there is a leading phase difference 23 of about 4 cycles with the cycle 21 of the clock signal as a unit.

FIG. 3 is a relationship table between the detected phase difference and the frequency division data preset in the counter in the PLL circuit according to the present invention. For example, if the phase difference + A is detected, + means that the comparison signal leads the input signal by A in phase. In this case, A corresponds to the quantized numerical data a with the cycle of the clock signal as a unit. For the counter that divides the clock signal,
(Standard value + a) is preset. Therefore, the frequency dividing counter counts the clock signal after the standard value + a,
Since the signal is output so as to change the waveform, the lead phase difference of the comparison signal is reduced within ½ clock cycle and then fed back from the first phase comparator 1 via the voltage controlled oscillator 3 and the counter 7. Due to the function of the circuit, it converges within a predetermined range. By the same operation, delay phase difference −B
In the case of 1, the frequency dividing counter is preset with (standard value −b) and then has a frequency dividing operation, and the delay phase difference of the comparison signal is eliminated. The standard value is the input signal 10 when the counter 7 counts the clock signal 11 by the value.
The value is set to be the cycle of. Incidentally, the clock signal 11 is 4 fsc (color subcarrier 3.58 MH
4 times z), the standard value of the counter is 910. When the phase difference detected by the second phase comparator 4 is within a half clock cycle, the standard value is preset in the counter 7.

[0009]

As described above, the present invention provides a PLL circuit which, when supplied with an input (reference) signal, can output a clock signal phase-synchronized with the input signal within a predetermined time. . Therefore, in clear vision or the like, it is possible to supply a stable clock signal that is phase-synchronized with the input horizontal synchronizing signal within a predetermined time such as channel switching and power-on.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram showing a phase difference of a comparison (feedback) signal with respect to an input (reference) signal in a PLL circuit according to the present invention.

FIG. 3 is a relationship table of detected phase differences and frequency division data preset in a counter in the PLL circuit according to the present invention.

FIG. 4 is a block diagram of an embodiment of a conventional PLL circuit.

[Explanation of symbols]

 1 First Phase Comparator 2 Low-pass Filter 3 Voltage Controlled Oscillator 4 Second Phase Comparator 5 Digital Converter 6 ROM Table 7 Counter 10 Input Signal 11 Clock Signal 12 Feedback Signal 13 Preset Data 21 Clock Signal Cycle 22 Delay Phase difference 23 Leading phase difference 25 Detected phase difference 26 Data for frequency division preset in the counter 31 Phase comparator 32 Low pass filter (LPF) 34 Voltage controlled oscillator 37 Counter 40 Input signal 41 Clock signal 42 Feedback signal

Claims (2)

[Claims] 1. A first phase difference detecting means for detecting a phase difference between input signals and outputting a signal corresponding to the phase difference, and a signal output by the phase difference detecting means for inputting and converting into a DC voltage. A low-pass filter that outputs the signal, a voltage-controlled oscillator that is connected in series to the low-pass filter and that generates a predetermined signal that is controlled by the DC voltage and outputs the signal, and an output signal of the voltage-controlled oscillator. A PLL comprising a frequency dividing means which is connected to the phase difference detecting means and is feedback-connected to the phase difference detecting means.
In the circuit, a second phase difference detecting means that is connected in parallel with the first phase difference detecting means, detects a phase difference between input signals, and outputs a signal according to the phase difference, and the second position difference detecting means. Means for inputting the phase difference signal output by the phase difference detecting means, converting it to digital data and outputting it, storage means for outputting predetermined data stored according to the input digital data, and data supplied from the storage means According to the digital data obtained from the signal output based on the detection result, the phase difference between the signals input by the second phase difference detection means is detected. Predetermined data stored in advance is taken out from the storage means, and the frequency division ratio of the frequency division means is changed based on the data so that the reference signal is frequency-divided and then fed back. Reduces the phase difference of the signal, PLL circuit for causing phase synchronized with the reference signal is input to the feedback signal. 2. The PLL circuit according to claim 1, wherein the frequency dividing means is a counter capable of presetting data output from the storage means.