JPS61214667A - Pulse generating device - Google Patents

Abstract

PURPOSE:To generate a pulse signal synchronizing exactly with a synchronizing signal of two kinds of long and short periods by providing a phase locked loop circuit for generating a clock synchronizing with a synchronizing signal of the short period, and a circuit for generating a pulse, based on the clock and a long period synchronizing signal. CONSTITUTION:A pulse generating circuit 7 generates various pulse signals by setting a signal outputted from a VCO 5f as a clock, and also setting a rise of an output signal of a frequency divider 6 as a rise of HS of a video signal. On the other hand, VS which has been separated by a vertical synchronization separating circuit 3 is also supplied to the pulse generating circuit. This VS is brought to sampling at every rise of the output signal of the frequency divider 6, VS is detected by synchronizing with HS, and a pulse generating signal which is synchronized with VS is obtained. By this pulse generating signal and the output signal of the frequency divider 6, a pulse signal which has synchronized with VS and HS can be outputted. In this way, the pulse signal which has synchronized completely with HS and VS is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a pulse generator, and more particularly to a device for generating pulses synchronized with synchronization signals having two types of periods, long and short.

<Prior art> Video signals generally include a horizontal synchronization signal (H3) and a vertical synchronization signal (VS), and devices that handle such video signals utilize pulse signals synchronized with these two types of synchronization signals. There are many opportunities.

Conventionally, as a device for generating this type of pulse signal, an H9. VS
The video signal and pulse signal were reset and the phases of the video signal and pulse signal were matched.

<Problems to be Solved by the Invention> However, in the pulse generator as described above, the clock output from the oscillator and the video signal are not necessarily synchronized, so the output pulse may vary depending on the timing of the reset. This results in a time axis error corresponding to the efflock. Therefore, in order to minimize this time axis error, it is necessary to make the oscillation frequency of the oscillator extremely high.

Therefore, it is necessary to separately prepare high-frequency circuit components for each part of the device. Furthermore, since high-frequency signals are handled, the influence on peripheral circuits is large, and in order to prevent this influence, it is necessary to provide some kind of shielding means.

In view of the above-mentioned problems, an object of the present invention is to provide a pulse generator capable of generating pulse signals accurately synchronized with synchronization signals of two types of long and short periods without handling Takaoka wave signals. .

<Means for Solving the Problems> In order to solve the above-mentioned problems, the present invention provides a phase-locked loop circuit for generating a clock synchronized with a short-period synchronization signal, and a phase-locked loop circuit for generating a clock synchronized with a short-period synchronization signal, and a long-period synchronization circuit with the clock. A circuit for generating pulses based on the signal is provided.

<Function> By synchronizing the generated clock itself with the short-period synchronous signal as described above, it is possible to obtain pulses accurately synchronized with the short-period synchronous signal and the long-period synchronous signal without increasing the frequency of the clock. .

<Embodiment> FIG. 1 shows a pulse generator as an embodiment of the present invention. In FIG. 1, l is a terminal to which a video signal is input;
2 is from the input video signal! 3 is a horizontal synchronization separation circuit that separates vS from the input video signal.
4 is a phase comparator; 5 is a voltage controlled oscillator (VC) that oscillates at an oscillation frequency according to the output error signal level of the phase comparator 4, especially its low frequency component;
o), 6 is a frequency divider that divides the output of vCO.1 The output of frequency divider 6 is fed back to phase comparator 4, and HS
The phase is compared with 7 is a pulse generation circuit that generates pulses using the output of vCO5, the output of frequency divider 6, and vS.

The phase of HS separated by the horizontal synchronization separation circuit 2 is compared with a signal having the center frequency of the horizontal scanning frequency (fH) generated by the frequency divider 6. The error signal obtained from the phase comparator 4 controls vCO which oscillates at the center frequency nfH (n is an integer), so that the output signal of the frequency divider 5 and HS become signals with the same phase and frequency. . By doing this, for example, the timing of the rise of i(S and the rise of the output signal of the frequency divider 5) is made to match.These phase comparator 4, vCO5, and frequency divider 6 constitute a phase locked loop, so-called PLL. Needless to say, they are doing so.

The pulse generation circuit 7 uses the signal output from the vCO 5 as a clock, and uses the rise of the output signal of the frequency divider 6 as the rise of the HS of the video signal to generate various pulse signals. On the other hand, vS separated by the vertical synchronization separation circuit 3 is also supplied to the pulse generation circuit 7. This vS is sampled every time the output signal of the frequency divider 6 rises, and vS is detected in synchronization with HS to obtain a pulse generation signal synchronized with vS. Using this pulse generation signal and the output signal of the frequency divider 6, a pulse signal synchronized with VS and HS can be output. In this case, since vS for pulse generation is a signal synchronized with HS, it is ±1 to vS separated from the video signal.
Even if there is a variation in the 72 horizontal scanning period, the output signal of the frequency divider 5 always becomes the reference signal, so the output signal of the pulse generation circuit 7 is not affected.

With the configuration described above, it is possible to generate pulse signals completely synchronized with HS and VS. In addition, the frequency of the clock at this time may be several times that of the HS. In other words, since a clock synchronized with the HS is used, a clock that satisfies only the phase accuracy required by the output pulse is sufficient. itself is synchronized to the video signal, so
The time axis error of the formed pulse signal is extremely small.

<Effects of the Invention> As explained above, according to the present invention, it is possible to generate pulses that can accurately form a pulse signal synchronized with a short-period synchronization signal and a long-period synchronization signal without increasing the frequency of the generated clock. What you get is the device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a pulse generator as an embodiment of the present invention. 2 is a horizontal synchronization separation circuit that separates a horizontal synchronization signal as a short-period synchronization signal; 3 is a vertical synchronization separation circuit that separates a vertical synchronization signal as a long-period synchronization signal; 4 is a phase comparator; 5
is a voltage controlled oscillator, and 6 is a frequency divider.

Claims (1)

[Claims] A device for generating pulses synchronized with synchronization signals having two types of long and short periods, the device comprising: a phase-locked loop circuit for generating a clock synchronized with the short-period synchronization signal; the clock and the long-period synchronization signal; and a circuit for generating pulses based on the pulse generator.