SU884106A1 - Device for clock synchronization and discriminating of pulse train - Google Patents

Description

(54) DEVICE OF TACT SYNCHRONIZATION AND ISOLATION OF A PULSE PULSES

I

The invention relates to a pulse technique, in particular, to a generator that temporarily assigns an asynchronous signal to a clock frequency and, in addition, generates a series of pulses, the number of which depends on the duration of the asynchronous signal, and can be used for pulse-counting information.

Known shaper series of pulses, containing two trigger 1.

The disadvantage of this device is that it does not have an output; the first synchronized pulse of each transmitted pulse train is formed on KotopoM.

The closest to the proposed technical essence and circuit solution is a clock synchronization device containing two triggers AND a match element, one input of which is connected to the synchronization time and the C input of the first trigger, two other inputs connected to the direct outputs of the first and second trigger , and the output is connected to the output bus and the C-input of the second trigger, S-VHBD Kotoroto is connected to the forward output of the first trigger, the D-input of which is connected to the R-input and to the input bus, and the sive output is connected to the D-input on the second about tripaC2J,

A disadvantage of the known clock synchronization device is that it cannot form bursts of pulses at the output.

The purpose of the invention is to expand the functional capabilities of the device, namely, simultaneously with the formation

10 synchronized pulse to pass on the output of a burst of pulses, the number of which depends on the duration of the asynchronous signal.

The goal is achieved by the fact that It is a clock synchronization device and a burst selection containing two flip-flops and a matching element, one input of which is connected to the synchronization width, two other inputs connected to the direct outputs of the respective triggers, is outputted to the first output bus and

The M C input of the second trigger, whose S input is connected to the forward output of the first trigger, for which the B input is connected to the input line, and the inverse output connected to the D input of the second trigger, is entered the NOT element and the second coincidence element, the output is connected to the second output bus, the first input is connected to the direct output of the first trigger, and the second input is connected to the synchronization bus and to the inputs of the HE element, whose output is connected to the C input of the first trigger.

FIG. I shows a functional diagram of the proposed device for clock synchronization and pulse burst allocation; in fig. 2 - timing charts of the device.

The device contains triggers I and 2, the element is NOT 3, the elements of coincidence 4 and 5, the input bus 6, the bus 7 synchronization, the output bus 8 and 9.

The device works as follows.

in the initial state on the input bus b - low level, clock synchronization enters the synchronization bus 7 (Fig. 2a), at the output of the element HE 3 (Fig. 2c) pulses inverse clock, trigger I in the zero state, low level pr My output overlaps the elements of coincidence 4 and 5 and sets trigger 2 at the S input to a single state, on output buses 8 and 9 (FIG. 2, f) high levels. Trigger 1 is in standby mode. The input asynchronous pulse (Fig. 26) sets a high level at the D input of the trigger — a high level and a level difference from low to high at the output of the HE element 3 and, therefore, at the C input, with the trigger 1 is set to one (Fig. 2d, d). A high level of direct trigger output 1 permits the passage of clock frequency pulses from bus 7 through coincidence element 5 to output bus 9 (Fig. 2e). At the same time, only one pulse passes through the coincidence element 4 to the output bus 8 (Fig. 2g). At the end of the output pulse on the output bus 8, a difference is generated from a low level to a high one, according to which trigger 2 (at its D input low level of the inverse output of trigger 1) is set to the zero state (Fig. 2h) and the low level of the forward output overlaps match element .4. At the end of the input signal on the input bus 6 (Fig. 2 b), trigger 1 returns to the zero state

(Fig. 2 g, d) if there is a drop from a low level to a high at the C input, the HE-3 element coming from the output (Fig. 2 c). The low level of the single output trigger 1 sets the trigger 2 on the S-input

in one state (fig. 2h) and elements of coincidence 4 and 5 to the initial position. When the next input pulse arrives, the process repeats.

Thus, in the proposed device. with the introduction of an additional element of coincidence, the possibility of simultaneously issuing signals on different front tires appeared; one is only the first synchronized pulse, the other is a pack of synchronized pulses, the number of which is determined by the duration of the input asynchronous pulse. This allows you to extend the functionality of the device.

Claims (2)

Invention Formula A clock synchronization and burst selection device comprising two triggers and a matching element; one the input of which is connected to the synchronization bus, the other two inputs are connected to the direct outputs of the respective flip-flops, and the output is connected to the first output jack and to the C-input of the second flip-flop, the S-input of which is connected to the forward output of the first flip-flop, which has a D-input is connected to the input bus and the inverse output is connected to the D input of the second trigger, characterized in that, in order to expand the functional capabilities of the device, an HE element and a second matching element, the output of which is connected to the second output bus, is inserted into it od Cpd yen to direct output of the first flip-flop and a second input connected to the synchronization bus and to the input of NOT circuit whose output is connected to the C-input of the first flip-flop. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 595851, cl. H 03 K 3/64, 1978. 5 2. USSR author's certificate No. 544115, cl. H 03 K 5/13, 1977 (prototype). a 5 -Tl iJ JTJTJTrunLnLr I II Figure 2 TXUnJlJlJnjaJlJTnJTJb I I II b JMI 1 I I 3 njiJi njTJijajnjiJij IIII