SU932602A1 - Random pulse train generator - Google Patents

Description

I

The invention relates to a pulse technique and can be used in computing.

Known random signal generator containing a random sequence sensor and shift register 1.

However, the generator has a rather low speed.

A generator of random sequences is known, containing sequentially connected generators of random signals, a block of elements AND, a shift register and a block of coincidences, and a generator of clock pulses with a trigger.

This generator also does not have a sufficiently high speed.

The purpose of the invention is to increase the speed of the generator.

The goal / goal is achieved by the fact that a random pulse sequence generator containing a clock pulse generator.

random pulse generators, the outputs of which through the corresponding element I are connected to the bit inputs of the shift register, are introduced — the inverter and the series-connected

.5 a deLitel counter and a decoder, the first output of which is connected to the inputs of random pulse generators, and the second output is connected to the second inputs of I elements, the counter 10 of the divider is connected to the output of the clock pulse generator and through the inverter to the clock register of the shift register.

The drawing shows a functional diagram of a random pulse sequence generator.

The generator of a random pulse sequence contains the generators of 1 random pulses, the elements of AND 2, the shift register 3, the generator of k clock pulses, the counter-divider 5, the decoder 6, the inverter 7, the output bus 8.

For the generator to work, it is necessary to have uncorrelated sequences at the outputs of generators 1 and the delay in issuing each character of information from the outputs of generators 1, due to their circuit design, should not exceed the value

N-T-t,

where T is the period of the clock frequency Fy, t is the duration of the recording pulse.

The generator works as follows.

From the generator 4 clock frequency F US; blunt to the input of counter-divider 5 and inverter 7, the states of counter-divider 5 are decrypted by decoder 6, from the first output of which each generator 1 receives polling signals with a frequency N times lower than the clock frequency Fj of the generator 1. The sequences from the outputs of generator 1 are fed to the first inputs of the corresponding elements I 2, the second inputs of which receive a write pulse from the second output of the decoder 6. The pulses from the outputs of the elements I 2 control the unit installation inputs (S-inputs stvuyuschih bits of register 3, to the clock input of which is inverse arrives, clock frequency output from the inverter 7 and the output from the final discharge registry random sequence generator is fed to an output bus 8.

Claims (2)

Invention Formula A random pulse sequence generator containing a clock pulse generator, random pulse generators, the outputs of which are connected to the bit inputs of the shift register through the corresponding element I, characterized in that, in order to increase the generator speed, an inverter and a serially connected counter-divider are introduced into it and the decoder, the first output of which is connected to the inputs of random pulse generators, and the second output is connected to the second inputs of the elements And, the input of the counter-divider is connected n to the output of the clock generator and through the inverter to the sync input of the shift register. Sources of information taken into account in the examination 1. French patent N, cl. H 03 K 3/8, 1973. 2. USSR author's certificate I, cl. H 03 K ZU8, 1975. F MF Sc) C4J