SU737984A1 - Device for exchange with magnetic disc-based storages - Google Patents

Description

f6 is connected to the data readout output of the storage drive, the information hbdbm is the first bit of the shift register, and the synchronization output is connected to the first input of the OR element, the output k6 is connected to the input of the shift register and one of the pulse, you controlling the reception of codes in the device and their issuance are connected to the corresponding to yttpaTeilW of the inputs of the receive and output valves kbda, the output of the last bit of the shift register is connected to the information input of the recording data generation unit , the sync input is connected to the generator output of the reference clock, and the write sync pulses are connected to the second input of the OR 2 element.

A disadvantage of this device is that the accuracy of matching information due to the deviation of the signal parameters EK time is low when using the recording method without returning to zero.

The purpose of the invention is to increase the reliability of the read information by eliminating the influence of the time deviation of the MeHHfcJX parameters when reading information.

The goal is achieved by the fact that a code analysis block and a variable delay block are entered into the device, with the inputs of the code analysis block associated with the forward and inverse outputs of the last bit of the shift register, and the e outputs with the control inputs of the delayed variable block, informational and synchronizing The inputs ft from op ogb are connected with c6otvotstvёvtgb to yyadamy data recording and sync pulses of the recording unit of the data output of ayyisi, and the output - to the data input of the recording drive on magnetic disks.

FIG. 1 is a block diagram of the device; in fig. 2 shows an example of the technical implementation of the code analysis block and the variable delay block; in fig. 3 is a timing diagram: explaining the formation of a deviation of the temporal parameters of the signals from the information institute.

The device contains gates 1 of a parallel code reception, a double-bit register, gates 3 of a parallel code, block 4 for separating informational and synchronous signals, element 5 OR, counter 6, block 7 for recording data, generator 8 reference clock pulses, block 9 code analysis, variable block 10, hold.

Block 9 is a code code and block 10 of variable delay (Fig. 2); the elements 11, 12, 13, 14, and 15, the elements OR 16 and 17, triggers 18, 19, and 20, the delay element 21 are in place ..

In the time diagram (Fig. 3), the following designation is accepted:

, is the period of the following synchronization signals in the write and read mode, respectively;

Tj:, t is the delay time of the information signals relative to the synchronization signals in the write and read modes, respectively;

t-j, is the relative delay time of the Signal when reading due to the finite rise time of the signal in the read head;

at- deviation of the signal delay time when reading due to the superimposed synchronization signals and information signals;

IT is the deviation of the period of the synchronization signals during the reading due to the superposition of information signals and synchronization signals.

When using the non-zero recording method, a sequential binary code coming from a magnetic disk drive is characterized by the fact that the delay between the information signals and synchronization signals and between the synchronization signals themselves changes depending on the interlacing of the values of binary bits. The values of these delays vary widely. In addition, the durations of the signals themselves vary considerably (up to 35%).

FIG. Signals for recording are shown; in fig. 36 shows plots of currents in a read / write head; in fig. Sv depicts the resulting signal from the read head; in fig. Зг - output signals from the accumulator.

When storing information on magnetic disks, the signal structure is as follows. Spiral clock pulses are formed along a spiral-shaped generator with a constant period of following T (Fig. 3). The logical information is placed in the middle between the sync pulses, and the logical unit corresponds to the formation of an STS signal, and the logical zero is its absence. When recording information, these signals are formed, and when read, they are separated.

In the process of reading information from a magnetic disk, a deviation occurs between the duration of the sync pulse period and the delay time of the 6th signal relative to the sync pulse.

Deviation Reaches such values that when processing signals from a storage device with a sufficiently high information recording density, the delay of the information signal relative to the synchronization pulses approaches the duration of the period of 5 consecutive clock pulses and the separation of clock pulses and information signals is impossible.

The deviations of the time parameters of the read signals occur with such alternations of information and synchronization signals when they are located in close proximity to one another, i.e., both signals with code 111 ... begin to shift in time, starting with the first information signal.

With the alternation of the signals of logical zero and unit 0101 ... there is a shift of the information signal and the following. Clock sync pulse. When transmitting codes 000 ... About the deviation of the duration of the period of the clock signal does not occur.

The device works as follows.

Before operation, all memory elements are reset to the zero state. The device can operate in two modes: the mode of recording information in the magnetic disk drive and in the reading mode. In this case, in the recording mode, depending on the combination of codes in the recorded information, the duration of the periods of the reference clock signals and the delay of the signals corresponding to the logical units are corrected relative to the reference clock signals.

In the recording mode, the parallel code from the device input through the parallel code reception valves is recorded in the shift register 2, the counter 6 is simultaneously reset. The clock sync pulses generated from the generator 8 signals of the reference clock pulses by the recording data generating unit 7 through the element 5 OR shift the information in the register 2 shifts. Coming from the output of the last bit of the shift register 2 and from the generator 8 reference clock pulses to the recording data generating unit 7, the signals form the write data code in the magnetic disk drive. Simultaneously generated in block 7 of the formation of the recording data, the clock signals through element 5 OR arrive at the input of counter 6. The conversion factor of counter 6 is selected taking into account the length of the exchange single word, overflow of counter b is used to receive a new code through gates 1 of parallel reception of the code per register 2. the recording process continues. When forming the data record, the last two bits of the shift register 2 arrive at the input of the code analysis unit 9, where the analysis of the specified situations of alternating signals of logical zeros and ones is performed. When a situation is detected where the timing deviation is possible, a control signal is received from the output of the code analyzing unit 9 to the input of the variable eduction block 10, which enables or disables the delayed fixed delay and the output of the variable delay unit 10

the delay of the signals that have undergone the forced reading of information is reduced compared to the nominal signal delays. Such an organization of the regime

o records provides compensation for the deviation of time parameters when reading information from the drive. In the read mode, the signals from the drive are not; magnetic disks are coming in

5 separating information and synchronization signals 4, at one of the outputs of which synchronization signals are formed, and at the other - information signals. The clock signals are fed through the OR element to the input that controls the shift of information in shift register 2 and to the input of counter 6, where the number of bits in the sequential read data code is counted. When it overflows you

, give the signal to the control input of the valves 3 parallel issuance of the code,

Which carry out the task of the code from shift register 2. Information signals from the output of division block 4

0 code is sent to infomation, the input of the first bit of register 2 shift. Thanks to the recording, si information is reduced delays of information signals relative to

5 sync pulses and periods of synchro pulses, the resulting deviations of the time parameters are compensated, and the relative position of the signals approaches the nominal, reading and separation of signals can be performed with high reliability.

The cited {fig. 2) functional diagrams of block 9 code analysis and block. By the 10 variable delay, a possible variant of the technical implementation of these blocks is disclosed. Incoming. From the last two bits of the register 2, the shift codes to the inputs of 31 records And 11, 12 and 13 and OR 16 provide the switching of the triggers 19 and 18. Trigger

18 provides the change in the delay of the sync signals when transmitting signals of code 010 when it is necessary to reduce the delay of the sync signal following the signal of the logical unit, ci. If a situation arises when a logical zero follows

.signal of logical unit, trigger

19 is set to single state by a signal from an element output

0

11 I., ..

A change in the signal delays relative to the nominal values is not made, or a count of 000 is transmitted. O, so the signal from the output5

s ijieMeHTa 3 AND / which foryru with the alternation of characters, triggers 18 and 19 are set to the zero state. A trigger from the trigger 19 of block 9 of the analysis of the 9 k 9 is sent to the information input of the trigger 20 of block 10 of the variable per clock. The Nagoniznizcht Gt Yezhg r alt ptnrnrnrnrrrrrrrrrrrrrrrrnrnrnrnrrrrrrrrrrrrrrrrrrcrrrrrrrrrrrrcrrrrrrrrrrcrrrrrrrrrrrrrcrrrrrrrrrrrrrrcrcrrrrrrrrrrrrrrrrrcouzkouhou Food Alternator 8 LUO {5NVSVS, and that these signals are already being formed that -cccccccc 1 shorter duration. signal delays. When the signal of a logical unit is shown on the gate; 6de of code analysis, the trigger JJ loses the variable delay and sets the current state and data

Recorded from the output of the block 7 of the Fortlaying of the Record through the element of the CZD and the element of the input of the block of the overeaty delay for the: Into the drive. If the trigger 2SGnakho et-FTiyjieBbM is nesto, then yKnnke. Records via element 14 And pbc uygiootdelaying 21, to & jpHS o6e ire4 Hiae; T shift the signals to nominal values.

L BESH VChNVaet; the extension of the scatter of information and information and will be at 2e-W% of the content of the information, while providing the separation, symbols ,.

Claims (2)

1. Drozdov, E.A., et al. Fundamentals of the construction and computational systems for computing systems. M., Energie, 1973, p. 1bЗ. 2.Jsabean 3 .G. High speed. High Density Digital Recording Telemetry Joresnal, 1972, august (September), p. ll-lSv . i - ..; -.1, i -J -, - „- rt