SU1688435A2 - Device for monitoring of communication channel - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the accuracy of control by operating in a network of channels. On transfer using the encoder 5 addresses. the address generator 6 and the address control block 7 form the address of the subscriber of the opposite station for which the test combination is intended, complement the signal of the test combination formed by sensor 1, driver 2, block 3 and driver 4, with information about the address of the subscriber and transmit to the input of the controlled channel 24 connections. Through the network of channels, the test combination is transmitted to all subscribers of the network. At the reception, all subscribers receive the address information and compare the received address with their control address. The result of the comparison by block 23 goes to block 22. If the addresses are not equal, the analysis is blocked, if it is the same, the erroneous bits are received and detected. 1 il. fe

Description

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The invention relates to telecommunications, can be used to control a network of data transmission channels and is optional by author. No. 1592953.

The purpose of the invention is to improve the accuracy of control by operating in a network of channels.

The drawing shows an electrical block diagram of a device for controlling a communication channel.

The device for monitoring the communication channel contains in transmission: sensor 1 test text, shaper 2 repetitive numbers, cycle control block 3, back reader shaper 4, address encoder 5, address shaper 6, address control block 7, And 8 and 9 elements and the element OR 10; on reception: analyzer 11, pulse generator 12, check text sensor 13, repeat number generator 14, cycle control unit 15, reverse reading unit 16, comparison unit 17, registration unit 18, number comparison unit 19, address encoder 20, driver 21 addresses, address control unit 22, address comparing unit 23 and sensor control unit 24.

The device works as follows.

Sensor 1 according to the signal A request of a regular combination (30K) forms the Start of Exchange (BUT) signal, which goes to the cycle control block 3 and the address control block 7.

According to this signal, block 3 generates the write enable signals to the register and clock pulses (TI), which are fed to the shaper 2 of the repeated numbers and the shaper 4 of the reverse reading. According to these signals, the number assigned to the test combination by sensor 1 is rewritten in parallel in direct reading into shaper 2 repeatable numbers and in reverse reading into shaper 4 in reverse reading. According to the NO signal, the address control block 7 generates two signals: an enable signal The resolution of address writing (Рш Зп Ад), arriving at the input of And 9, and a forbidding signal block the passage of information through it. On the decline of the signal BUT coming from the sensor 1. The cycle control unit 3 generates a sequence of TI signals that arrive at the counter K of the address bits of the address control block 7.

The address of the subscriber to whom the test combination is intended is set on the address encoder 5, encoded

and provide the register with the address K of the driver 6 addresses. On a signal, the resolution of the register record (Рш Зп Рг), coming from the cycle control block 3, occurs

parallel writing of the address in the address driver 6 and the test combination in the driver 2 repeat numbers. According to the TI signals from the cycle control unit 3, the system produces

0 all address bits from register 6 of the address maker to another input of the AND 9 element and then through the OR 10 element to the input of the controlled channel of the communication network. The input element of the circuit And 9 at this time comes

5 enable signal Рш Зп Hell.

The passage of the test combination from the output of the generator 2 duplicate numbers through the element OR 10 is blocked at the input of the element 8 by the input of the monitored channel 25 of the communication network. At the same time with the TI address information, the number of pulses of the TI signal is counted by the counter of the block 7 address control, which, counting out K pulses (respectively, K address resolution), prohibits the passage of address information through AND 9 element by setting on its other input a prohibitory signal and

0 Рш Зп Hell. and permits the passage of the test combination from the output of the former 2 duplicate numbers through the element AND 8 by setting at its input the enable signal ZAPR Zp Ad, By

5 this signal, coming from the address control unit 7 to the cycle control unit 3, removes the TI signal blocking, by which the test pattern is sequentially outputted from the register of the former 2 repeating numbers through the AND 8 element and the OR 10 element to the input of the monitored channel 25 of the network connection. On reception, address encoder 20, address driver 21, and control block 22

5 address work similar to the corresponding blocks 5-7 on the transfer.

The address information is transmitted from the output of the controlled channel 25 of the communication network through the analyzer 11 to the address

0 input of the comparison circuit of address comparison block 23. To the other address input of the comparison circuit of the same block comes the control address from the output of the receive address 21 driver. If the address does not match

5 of the test combination with the control address (foreign address), the address comparison block 23 outputs a inhibitory signal Resolution Analysis (PhR Analysis) to the input of the sensor control block 24. The Rsh Analysis signal prohibits the issuance of 24 signals from the block Permission to exchange (Rsh Odm) and Permission to write a counter (Rsh Zp Sc) in the sensor 13 of the control text. At the same time, further analysis is blocked, and the formation of the next control combination is also prohibited.

If all the address bits of the test combination coincide with the control address (your address), the output of the comparison signal Rn Analysis is output from the comparison circuit of the address comparison unit 23 to the control circuit of the sensor control unit 24.

After counting the K pulses of the TI signal, the counter of the address control unit 22 generates the inhibit signal Pm 3p Ad and outputs it to the address comparison unit 23. The signal Rsrn Ad ad prohibits the comparison of addresses in address comparison block 23, and outputs a single pulse signal End of Address Information (KAI), according to which the control circuit of the sensor control unit 24 generates signals RsrBMB and Rsnp Mfr. According to these signals, the sensor 13 of the control text forms the next M-digit number of the control combination. For the entire time of receiving and analyzing address information, the comparison circuit of the comparison block 17 is blocked from false analysis by the inhibiting signal ZAPR Zp Ad, coming from the output of the address control block 22.

As a control signal from the communication channel, a signal is received. The pulse of the start of the combination (INK) is fed to the inputs of the analyzer 11 and the sensor 13. By the signal of the INC, the analyzer 11 is reset and generates a signal Turning on the generator 12, and the sensor 13 generates a signal which enters block 15 and sets it back to its original state. In addition, using this signal, block 15 generates the recording enable signals to the register and the GI, which are fed to the shaper 14 and the shaper 16, as well as the synchro shift signal (SISv) and the write signal to the register, which are fed to the analyzer inputs 11. The signals TI and SI Shdv are formed from signals from generator 12 to block 15. At block 17, simultaneously with the test combination from analyzer 11, a control combination from generator 14 arrives, and the result of non-comparison accumulates and enters analyzer 11. After counting 2 Ofs signal pulses SI analyzer 11, register switching occurs, whereby it is recorded in the number of test combinations of forward and reverse reading. In addition, the first M bits (direct reading number) are stored in the analyzer 11. After this, the output of the analyzer 11 is blocked and at its output the result of the comparison is obtained

5 test combination with all its subsequent bits. The result of the incomparability is remembered.

The result of the survey pulses of the signal coming from the generator 12, the analyzer 11 and the block 17, is decrypted by the analyzer 11 and the result is memorized. At the end of the control combination, block 15 generates a signal for the end of the cycle, which is fed to the analyzer 11, and also to the generator 12 to switch its operation mode.

If the numbers of the received test combination both in the forward and reverse reading are equal to each other and are equal to the numbers

0 direct and reverse reading of the control combination, then a decision is made about the correctly received test combination, with signals such as Error bits, Error combinations,

5 Inserted combinations, and Missed combinations are not received in block 18. As a result of a survey of the analyzer 11, an Equal To signal is generated, which sets the analyzer 11 and the generator 12

0 the initial state preceding the receipt of the next test combination from the monitored channel 25. If the numbers of the received test combination va are equal to each other, and the same

5, comparing the test and control combinations by block 17 revealed incomparability, it is decided that the combination was wrong.

In this case, the number of incomparisons found in block 17 is output to block 18. After that, the analyzer 11 and the generator 12 are reset, as after the Equal to signal. If the numbers of the test combination are equal,

5 and a one-by-one comparison of the test and control combinations by block 17 revealed an incomparison, then a decision is made about disrupting the order of numbers of test combinations, i.e. you are introduced

0 event inserted or missed combinations. In this case, the numerical value of the noncomparisons recorded by the accumulator of the comparison unit 17 is erased.

Concretization of the inserted or passed combinations is carried out in block 19 by subtracting from the number of the control combination coming from the generator 14 of the number of the test combination coming from the analyzer

11. If the difference is positive, then the received test combination is inserted and the unit is recorded in block 18, and from block 19 sensor 13 receives a signal to block the passage of the next signal, Zn Sc. In this case, in the sensor 13, the old number is retained when receiving the next test combination, and the analyzer 11 and the generator 12 are reset.

If the difference is negative, it indicates the omission of a certain number of test combinations. Their absolute value is determined by block 18 by the signals of the generator 12 and outputs in the form of the corresponding number of pulses to block 18. At the same time, by the signal of block 19 to sensor 13, the number of the test combination from the analyzer 11 is parallel to the sensor 13. After that, as in In the case of inserted combinations, the analyzer 11 and generator 12 are reset.

Claims (1)

Claims of the Invention A device for monitoring a communication channel according to the author. No. 1592953, characterized in that, in order to increase the control accuracy by operating in a channel network, the first output of the duplicate number generator is connected to the monitored communication channel through the first AND element and OR element entered in series, the address control unit is entered and sequentially the connected address encoder, the address driver and the second element AND, the output of which is connected to another input of the IL-element AND, another input is connected to the first control output of the address control unit, the second output control of which is connected to another input of the first element This And, the clock input and the output of the write inhibit address are connected respectively to the clock output and the write inhibit input of the cycle control unit, and the control input is connected to the control output of the test text sensor, the clock output and the write enable output of the cycle control unit are respectively connected to the clock input and the enable input of the address address writer, and on reception the address control block and the serially connected address encoder, address builder, address comparison block and date control block The output of which is connected to the fifth corresponding inputs of the control text sensor, the input of the start of the combination is combined with the input of the beginning of the analyzer combination, and the second input is connected to the first control output of the address control block, the clock input of which is connected to the clock output of the cycle control block, the control input is connected to the second control output of the pilot text sensor, the second control output is connected to the fourth input of the comparison unit, and to the fifth input of the analyzer, the third control The output output is connected to the control input of the address comparison block, the clock input of which is combined with the analyzer's clock input, the output output of which is connected to the address input of the address comparison block, the exchange start input of which is connected to the second output of the control text sensor, clock input, write enable and the address input of the address driver is connected respectively to the clock output, the resolution output and the address output of the loop control unit.