SU1742825A1 - Multichannel device for interfacing computers - Google Patents

Abstract

The invention relates to computing and can be applied to local area networks. The purpose of the invention is to increase the reliability of the device. The goal is achieved by introducing a clock unit into a multi-channel device, each channel of which includes two amplifiers, two key blocks and a status register, and an asynchronous serial transceiver, an address block consisting of two decoder addresses of eighteen elements And and the twelve elements OR, and the command block consisting of a decoder, a delay element and a command register. 4 il.

Description

The invention relates to the field of computer technology and can be applied in local computer networks, in particular in distributed control systems with more than three subscribers.

Known radial connection of several computers in a distributed computer network. Peripheral computers (subscribers) are connected through a communication computer with communication lines of tens to hundreds of meters. The communication computer organizes the transit exchange of information for any pair of subscribers. The disadvantage of the system is that the communication of subscribers is achieved by complex hardware and software means of a computer.

In the well-known radial connection of subscribers, a relatively simple specialized device for interfacing computational means allows pair connections remote from each other.

COMPUTER. The switching operation of the device is controlled by the subscribers.

The disadvantage of the device is that it can directly connect only three subscribers.

A multichannel device is known for interfacing computer subscribers with a common highway, which is divided into sections by means of trunk key blocks whose channels are controlled. The channel serves to connect the corresponding computer to the trunk.

Each channel contains a priority acquisition node, an input address register, device status registers, bi-directional information exchange keys with a computer, a group of amplifiers, and a control node.

The channel and the corresponding computer connect the bus: groups of code inputs priori b

VI

4 N3 00 U SL

theta, groups of code inputs of the subscriber's address, input of the output of the output, busy signal of the trunk, group of outputs of the start of reception, group of information inputs-outputs, synchronization of input-output.

Any computer can, at a random time, switch its channel to any other computer channel in such a way that the section of the main line used will be isolated. In this section of the highway, information is exchanged between two connected computers. At the same time, the remaining part of the line can be used in a similar way for pairwise connections of other computers.

The drawback of the device lies in the complexity of its connection with the computer and the inability to use standard interfaces. This increases the likelihood of errors in the operation of the device, makes it difficult or impossible to interface with different types of subscribers, as well as its application in computer networks with the dispersion of subscribers within tens to hundreds of meters. In addition, since the interaction of the device with subscribers is not synchronized, the operation of the computing system is not free from conflict situations. The above features of the device indicate a lack of reliability of its work in networks with dispersed objects of computer technology.

The aim of the invention is to increase the reliability of the device.

In contrast to the known, the proposed device has an increased reliability of operation, since it, firstly, contains a smaller number of physical communication lines both in the trunk and, especially, between the channel and the computer, and, secondly, the centralized clocking of the channels reduces the likelihood the nature of the emergence of conflict situations in operations for the establishment and termination of communication between channels. This advantage increases with an increase in the number of subscribers, since in the prototype the number of trunk tires grows faster. In addition, the fact that the trunk, key blocks and channel matching blocks represent a unified combination circuit, which, especially in a compact design, prevents the preservation and development of random faulty situations, for example, from external interference, increases the reliability of the device. .

An introduction to the proposed device of a standard serial transceiver for communication of a channel with a computer allows to increase the distance between them to

hundreds or more meters, and also makes the device more suitable for interfacing computers of various types.

Unlike the prototype, in the proposed device, the exchange of information of a pair of computers can be carried out in opposite directions independently of each other, including simultaneously. This provides additional opportunities for addressing confidential situations in the dialogue of subscribers allowed by software, and in some cases it can increase the performance of information exchange between subscribers.

5 Thus, in comparison with the prototype, the field of application of the proposed device is expanded.

In practice, the proposed device can replace a communication computer in

0 local area network with a radial topology and distances between subscribers within tens to hundreds of meters.

Two 15-channel prototypes of the proposed device, manufactured by the company, are tested in an automated control system of the technological line for the production of heat-generating elements for fast neutron reactors. Distance between

0 interfaced control computers are 5–40 m. For the base case, to determine the economic efficiency from the implementation of the proposed device, an automated system was previously used in this process line, in which the interface of control computer subscribers performed communication computer (the complexity and lack of reliability of the software

The provision of interactive machine-to-machine communications with the mediation of a communication computer was the basis for the development of the proposed device.

The expected annual economic effect from the introduction of the proposed device in this process control system is about 260 thousand rubles. The main condition for obtaining this effect is a comparatively higher reliability of the control of the production line, which according to preliminary estimates makes it possible to reduce its possible time by 5% simply because of failures in the control system and accordingly additionally use highly efficient fuel in production. product.

In addition, the source of the expected cost-effectiveness is lower, in comparison with the base case,

the cost of developing software and hardware systems using the proposed device.

This goal is achieved by the fact that a multichannel device for interfacing computers contains n channels, each of which contains two amplifiers, two key blocks and a status register, with the first and second groups of information inputs and outputs of the 1st channel. The terminals (1 2, p-1) are connected respectively to the second groups of outputs and inputs (1-1) of the channel and the first groups of information outputs and inputs (1 + 1) of the channel, information input and output of the serial code of the 1st channels are the corresponding input and output devices and for connecting to the information output and the input of the corresponding computer, in each channel the input of the first amplifier and the output of the second amplifier are respectively the information input and output of the serial channel code, the first groups of information inputs and outputs of the first and second key blocks are respectively the first and second groups of information inputs and outputs of the channel, a clock unit is entered, jabixofl and j- whose output group 0 1, p) is connected respectively to the synchronization input and g The clock inputs of the j-ro channel and an asynchronous serial transceiver, a matching unit consisting of two address decoders, eighteen AND elements and twelve OR elements, and a command block consisting of a command decoder, delay element and the command register, wherein in each channel the first output of the status register is connected to the first inputs of the first and second And elements, the first inputs from the third to the sixth And elements are connected to the first output of the command register, the second output connected to The first inputs from the seventh to ninth elements are And, and the third output - with the first inputs of the tenth and eleventh elements And, the group of outputs and the first information input of the command decoder are connected respectively to the group of information inputs and the fourth output of the command register, the second inputs from the third on the eleventh elements And and the clock input of the command decoder form a group of channel clock inputs, the output of the third element And is connected to the direct input of the twelfth element And and the first input of the thirteenth element And, the output of which th is connected to a first input of AND and fourteenth forward entry fifteen member I.

the output of the first element OR is connected to the second input of the thirteenth element AND and the inverse input of the twelfth element AND, the output connected to the first information input of the state register, the first output of which is connected to the first direct input of the sixteenth element AND and the first inputs from the second to fourth elements OR, the output of the sixth element AND is connected to the first input of the seventeenth element AND, the output of the fifth element OR is connected to the first input of the eighteenth element AND, the first inputs of the sixth and seventh elements OR are connected to Respectively with the outputs of the first and second elements And, and the second inputs respectively with the outputs of the first and second decoders address, the first input of the second amplifier is connected to the output of the eighteenth element And, the second input of which is connected to the second input of the fourteenth and inverse elements of the fifteenth and sixteenth elements And and the output of the eighth element OR, from the first to the third inputs of the ninth element OR are connected respectively to the outputs of the sixth, ninth and eleventh elements AND, the reset input of the connection state register with the output of the tenth element OR, from the first to the third inputs respectively connected to the outputs of the eighth, tenth and seventeenth elements AND, the synchronized input of the command register is connected to the output of the eleventh element OR, the first and second inputs connected to the outputs of the fourteenth element AND and nine respectively the OR element, the second input of the seventeenth element AND is connected to the output of the twelfth OR element, the second output of the state register is connected to the second inputs of the third and fourth OR elements, controlling the input the first key block and the first input of the eighth OR element, the second input of which is connected to the third output of the status register, the second input of the second OR element, the third input of the fourth OR element and the control input of the second key block, the first and second inputs of the twelfth OR element are connected respectively the fourth and fifth outputs of the state register, the second to the fifth information inputs of which are connected respectively to the outputs of the seventh and sixth elements OR, the fifteenth and sixteenth elements AND, the second from the first to the fifth outputs of the status register are connected to the group of information inputs of the asynchronous serial transceiver, the information inputs and output of the serial code and the first group of outputs of which are connected respectively to the output of the first amplifier, the second input of the second the amplifier and the group of information inputs of the command decoder, the second information input of which is connected to the ready output of the asynchronous serial transceiver Also, through the delay element with the synchronization input of the receiver of the asynchronous serial transceiver, the clock input of which is the synchronization input of the channel, and the synchronous input is connected to the output of the ninth OR element, the second group of outputs of the first key block is connected to the group of information inputs and the synchronous input of the first address decoder , the first inputs of the first and fifth OR elements, the second input of the first AND element, the fourth input of the tenth OR element, and the second group of information inputs of the second block to The keys, the second group of outputs of which is connected to the second group of information inputs of the first key block, the group of information inputs and the synchronous input of the second address decoder, the second inputs of the second element AND and the first and fifth elements OR, and the fifth input of the tenth element OR, the third group of information inputs and the enabling input of the first key block is connected to the second group of outputs of the asynchronous serial transceiver, the third output of the status register and the outputs of the fourth, seventh And elements, the fourth about the OR element, the first amplifier and the output of the second element OR, the third group of information inputs and the enabling input of the second key block are connected respectively to the second group of outputs of the asynchronous serial transceiver, the second output of the status register, the outputs of the first amplifier, fourth and seventh elements And, the fourth element OR and to the output of the third element OR.

The clock unit introduced into the proposed device, as well as the asynchronous serial transceiver entered into each channel of the device, the command unit, the matching unit and the corresponding connections, simplify the interface and apply the standard radial interface between the channel and its corresponding computer. them, compared with the known device, the allowable distance. This makes it possible with a compact (in one instrument design)

device, to combine the advantages of the backbone and radial topology in a single-tier computer network built on the basis of the proposed

devices.

In contrast to the known device, the operations of establishing and terminating several simultaneously operating paired communications of subscribers are clocked centrally for all channels, thus achieving an increase in the reliability of the operation of the device.

Figure 1 shows the general scheme of the device; figure 2 - structural diagram of the channel;

5 in FIG. 3 is an exemplary embodiment of a clock unit; 4 shows an exemplary embodiment of the first key block.

A multichannel device for interfacing computers contains

0 (Fig. 1); n channels 1, each of which contains (Fig 2) two amplifiers 2 and 3, two sets of keys 4 and 5, and a state register b. The first group of information inputs 7 and outputs 8 of the 1st channel (I 2, p-1) is connected to

5 to the second group of informational, respectively, outputs 9 and inputs of the 10 (S) -th channel. The second group of information outputs 9 and inputs of the 101st channel is connected to the first group of information, respectively

0 inputs 7 and outputs of the 8 (1 + 1) -th channel. Information inputs 11 and output 12 of the sequential code of the {th channel are the corresponding input and output of the device for connection to the information output and input of the corresponding computer, with the input of the first amplifier 2 and the output of the second amplifier 3 on each channel being informational input 11 and output

0 12 serial channel code. The first groups of information inputs 13 and outputs 14 of the first key block 4 of channel 1 are respectively the first groups of information inputs 7 and outputs 8

5 of the 1st channel. The first groups of information inputs 15 and outputs 16 of the second key block 5 are respectively second groups of information inputs 10 and outputs 9 of the channel.

0 Output 17 and j-group of outputs 18 of the clock unit 19 Q fin) are connected respectively to the synchronization input 20 and the group of clock inputs 21-25 of the j-ro channel. An asynchronous sequential transceiver 26, an agreement block 27, consisting of two decoders 28 and 29 addresses, eighteen AND 30-47 elements and twelve OR 48-53 elements, and a command block 60. entered in each channel, consisting of a decoder 61 command, the element 62 delays and command registers 63, with each channel having the first output of state register 6 connected to the first inputs of the first 30 and second 31 elements And, the first inputs from the third 32 to sixth 35 elements And are connected to the first output of the command register 63, the second output connected from the first and the inputs 36 through the seventh ninth AND gates 38, and the third output - to the first inputs 39 of the tenth and eleventh

And, the group of outputs and the first information input of the decoder 61 commands are connected respectively to the group of information inputs and the fourth output of the register 63 commands.

The group of clock inputs 21–25 of the channel is formed respectively by the clock input 21 of the decoder 61 of the commands; the combined input 22 of the second inputs of the third 32, the seventh 36 and the ten that 39 elements And; the combined input 23 of the second inputs of the fourth 33 and eighth 37 elements And; a clock input 24, which is the second input of the fifth element AND 34; combined input 25 second inputs of the sixth 35, nineteen 38 and eleventh 40 elements I.

The output of the third element And 32 is connected to the direct input of the twelfth element And

41 and the first input of the thirteenth element And 42, the output of which is connected to the first input of the fourteenth element And 43 and the direct input of the fifteenth element And 44. The output of the first element OR 48 is connected to the second input of the thirteenth element AND

42 and the inverted input of the twelfth element AND 41, the output connected to the first information input of the state register 6, the first output of which is connected to the first direct input of the sixteenth element AND 45 and the first inputs from the second 49 to the fourth 51 OR elements. The output of the sixth element And 35 is connected to the first input of the seventeenth element And 46, the output of the fifth element OR 52 is connected to the first input of the eighteenth element And 47, the first inputs of the sixth 53 and seventh 54 elements OR are connected respectively to the outputs of the first 30 and second 31 elements And, and the second inputs - respectively, with the outputs of the first 28 and second 29 decoders addresses. The first input of the second amplifier 3 is connected to the output of the eighteenth element And 47, the second input of which is connected to the second input of the fourteenth

43 and inverse inputs of the fifteenth 44 and sixteenth 45 And elements and the output of the eighth element OR 55. From the first to the third inputs of the ninth element OR 56 are connected respectively to the outputs of the sixth 35, nine 38 and eleventh 40 elements And

The reset input of the 6 state register is connected to the output of the tenth element OR 57,

from the first to the third inputs respectively connected to the outputs of the eighth 37, tenth of the 39th and the seventeenth 46 elements

0 OR 58, the first and second inputs connected respectively to the outputs of the fourteenth element AND 43 and the ninth element OR 56.

The second input of the seventeenth element and

5 46 is connected to the output of the twelfth OR element 59. The second output of the state register 6 is connected to the second inputs of the third 50 and fourth 51 OR elements that control the input of the first key block

0 4 and the first input of the eighth element OR 55, the second input of which is connected to the third output of the state register 6, the second input of the second element OR 49, the third input of the fourth element OR 51 and the control unit 5 by the equal input of the second key block 5. The first and second inputs of the twelfth the OR element 59 is connected respectively to the fourth and fifth outputs of the state register 6, the second to the fifth information inputs of which are connected respectively to the outputs of the seventh 54 and sixth 53 elements OR, the fifteenth 44 and sixteenth 45 elements AND, the second From the first to the fifth outputs of the register 6, the state is connected to the group of information inputs 75 of the asynchronous serial transceiver 26, the information input 76 and the output 77 of the successive code and the first group of outputs 78 which are connected respectively, with the output of the first amplifier 2, the second input of the second amplifier -3, and a group of information inputs of the decoder 61 commands,

5, the second information input of which is connected to the output 79 of readiness of the transceiver 26 and through the delay element 62 to the synchronization input of the receiver 80 of the transceiver 26, the clock input 81 of which

0 is a synchronization input 20 of the channel, and the synchronization input 82 is connected to the output of the ninth element OR 56.

The second group of outputs 64 of the first key block 4. is connected to the group of information inputs and the synchronous input of the first decoder 28 addresses, the first inputs of the first 48 and fifth 52 OR elements, the second input of the first element AND 30, the fourth input of the tenth element OR 57 and the second group information inputs 65

the second key block 5, the second group of outputs 66 of which is connected to the second group of information inputs 67 of the first key block 4, the group of information inputs and the synchronous input of the second decoder 29 address, the fifth input of the tenth element OR 57, as well as the second inputs of the second element AND 31 and the first 48 and the fifth 52 elements OR.

The third group of information inputs 68 and the enabling input of the first key block 4 are connected to the second group of outputs 83 of transceiver 26, the third output of the status register 6 and the outputs of the fourth 33 and seventh 36 And elements, fourth element OR 51, first amplifier 2 and with the output of the second element OR 49. A third group of information inputs 69 and the enabling input of the second key block 5 are connected respectively to the second group of outputs 83 of transceiver 26, the second output of state register 6, the output of first amplifier 2, fourth 33 and sed 36 and forward elements, the fourth OR gate 51 and to the output of the third OR gate 50.

The clock unit 19 contains (FIG. 3) a node of the group elements I 70, a decoder 71 clocks, a decoder 72 channels, a counter 73 and a square pulse generator 74, the first output of which is the output 17 of the clock unit 19, and the second output connected to the counter input 73, the output buses of the lower bits of which are connected to the input of the decoder 71 cycles, and the most significant bits - to the input of the decoder channels 72, each output of which is connected to the combined control input of the corresponding group element And node of the group elements And 70. To each output A decoder 71 clocks are connected in parallel with the same number by number of bit inputs of all group elements AND of the node group AND 70. The group of outputs of each group element 70j of the node of group elements AND 70 is the corresponding group of outputs 18j of the clock unit 19.

Figure 4 shows the execution of the key block by the example of the key block 4. The inputs of the first group of information inputs 13 of the key block 4 are the first inputs of a group of elements And implemented by integrated circuits (IC) of type K155 OR1.

The outputs of this group of elements And form the second group of outputs 64 of the key block 4. The inputs of the second 67 and third 68 groups of information inputs of the key block 4 are respectively the inputs D 1 and D 2 of the multiplexer elements implemented on the IC type K555KP14. The first group of outputs 14 of the block of keys 4 is formed by the outputs of the group of elements NOT IC K155LN1. inverting output signals of multiplexer elements. The combined inputs Z of the multiplexer elements connected through the element NOT with the combined second inputs of the group of elements AND are the control input of the key block 4, and

0 combined inputs of V multiplexing elements - allowing the input of the key block 4.

Structurally, the key blocks 4 and 5 are not different from each other. In the above

In the 5th embodiment of the key block, each group of inputs or outputs has five buses for transmitting control and information signals (address strobe, prohibiting seizure, part limitation, information and termination of communication), as well as three buses for address transmission. This corresponds to the maximum number of channels in the device p 8.

As transceiver 26, for example, an integrated circuit of the type KR581BA1 (serial asynchronous transceiver) can be used.

The device works as follows.

0 There are six channel conditions. Accordingly, state register 6 can take one of six values. Each of the first five values corresponds to an information input and potential

5 G at the same (by number) output of register 6.

When a signal is applied to the sixth input (reset input), a potential O is set at all outputs of the register, which corresponds to the initial state of register 6, and when the command register 63 is reset, to the initial state of the entire channel 1.

Potential O from the first and second outputs of state register 6, past

5 through the OR 50 element on the enable input of the key block 5, the second group of information inputs 65 of this key block is connected to the first group of outputs 16 of this block.

0 Potential 0y from the first and third outputs of the state register 6, passed through the element OR 49 to the enabling input of the key block 4, connects to the first group of outputs 14 of this block the second

5 group of informational inputs 67 of these keys.

Potential O from the second output of register 6, which arrived at the control (inverse) input of key block 4, removes the blocking of transmission of input signals to its first 14 and second 64 groups of outputs, respectively from the second 67 and first 13 groups of information inputs.

The potential 0 from the third output of the state register 6, which arrived at the control (inverse) input of the key block 5, removes the blocking of the transmission of input signals to its first 16 and second 66 groups of outputs, respectively from the second 65 and first 15 groups of information inputs.

Thus, if all the channels 1 are in the initial state, the trunk buses, successively passing through all the channels, retain the potential O across the whole device.

In the proposed device, the points in time for establishing and terminating communication between the initiator channel and the destination channel are set by a clock unit 19, which in its output groups 18i to 18p outputs the clock series of control signals for all channels in turn. The control of the channel, and through it the device as a whole, from the computer side is carried out by commands, each of which consists of two sent bytes of consecutive and executive. The first is a sign of the team, the second contains its subject part. Immediately after the execution of each command, the channel sends a status byte to the computer, which contains information about the result of the command execution.

Three commands can be distinguished: Subscriber Channel Request (SQA), End of Communication (CS), and Program Channel Reset (PSK).

At the command of the SCA, the situation in the channel and in the section of the highway passing through this channel is analyzed, and in a favorable situation, a connection is established between the channel in question (in this case, the initiator) and the destination channel, the number (address) of which is specified in the second, executive command byte.

At the command of the CC, the destination channel and the initiator channel are reset. The CC command serves to complete the dialogue.

On the command of the UCS, only the channel directly connected to the computer that issued the command is transferred to its original state. The UCS command serves to reset the channel, for example, after a partial reboot of the system in a failed situation.

We show the operation of the channel in a session of two computers.

Consider the situation in which the initiator channel and the destination channel are in

the initial state, and the section of the highway between them is free.

The preparatory byte of the command coming from the computer by the serial code

The SSA passes through the initiator channel through its input 11 and amplifier 2 to the information input of the serial input 76 of the transceiver 26, in which the phasing and synchronization of the reception of the code message is carried out using pulse arriving at the clock input 81.

Upon completion of the reception of bytes on the first group of outputs 78 of the transceiver 26 and, therefore, on the group of information

The 5 inputs of the command decoder 61 sets the received code. Its coincidence with the command sign is checked by the byte reception end signal coming from transceiver readiness output 79

0 to the second information input 61 and, simultaneously, to the delay element 62.

Check for coincidence in the decoder 61 is implemented at the moment when the first clock pulse arrives at its clock input from the input 21 of the channel clock group (all the clock pulse enters this channel 1j through its inputs 21-25 from the corresponding group element I 70j through its group output

0 18j, as shown in FIG. 3). If there is no match, then, after receiving from the output of the delay element 62, the pulse to the synchronization input of the receiver 80 of the transceiver 26 and the subsequent removal from it

5, the output 79 end of readiness signal reception of the byte, the channel is ready to receive the next byte. The delay element 62 is configured from the condition of capturing in the time interval for checking at least one clock pulse arriving at the clock input of the decoder 61.

If a match with the command sign is detected, the decoder 61 sends to the register of 63 commands the code 0001, in which

5 of its fourth output, potential 1 is applied to the first information input of the decoder 61. Under this condition, the next byte received at transceiver 26 is regarded as the executive byte of the command and checked by the decoder 61 to match the code of one of the possible commands, followed by sending The register contains 63 commands of the decrypted code. In the case under consideration, when the executive byte of the PCA command is decrypted, the command register 63 sets the code 0011, at which the potential from the first output prepares the elements 32-35 through their first inputs to transmitting the clock pulses from the second to the fifth

entering the channel through its group inputs 22-25 groups of clock inputs. Low potential from the output of the element OR 48, meaning the absence of signals to prevent the capture on the group outputs 64 and 66, respectively, of the keys 4 and 5, opens the element And 41 on the inverse input. By the second clock pulse passing through the elements 32 and 41 through their second and forward inputs, respectively, state register 6 on input 1 is set to the first position. From the first output of the 6th state register, the high level signal passed the elements OR 49 and 50 through their first inputs to the enabling inputs of blocks 4 and 5, respectively, of the keys, thereby connecting the group inputs 68 to the outputs 14 and inputs 69 to the outputs 16, respectively of the blocks keys 4 and 5. The same signal, having passed the OR 51 element through its first input, then through group inputs-outputs 68-14 and 69-16, respectively, of the key blocks 4 and 5, establishes a high potential for prohibiting trapping on trunk buses.

Potential 1 from the first output of the state register 6 opens, on the first inputs, elements 30 and 31, preparing to receive a response signal of the site restriction, which is expected to arrive from the addressee on the corresponding buses from group outputs 64 or 66 key blocks, respectively 4 and 5.

The subscriber address stored in transceiver 26 after receiving the execution command byte comes from the second group of outputs 83 of transceiver 26 through the corresponding buses of group inputs-outputs 68-H and 69-16 of key blocks 4 and 5 to the trunk.

The third clock pulse, passed through the second input element And 33 through group inputs-outputs 68-14 and 69-16, respectively, of the blocks of keys 4 and 5, arrives at (trunk as the signal of the address strobe.

Suppose that the destination channel has a lordic number greater than the one under consideration.

In one of the channels, namely in the addressee channel, the addresses of the incoming and assigned to this channel will coincide. At the output of the decoder 28, a pulse is formed, which, having passed the OR 53 element through its second input, translates the state register 6 into the third position. Potential 1 from the third state register output 6 does the following:

closes the key block 5 at its control input;

pass through the element OR 49 through its second input to the block enable input

keys 4, connects the destination channel through the group inputs-outputs 68-14 of the key block 4 to the trunk section between the destination channel and the initiator channel (i.e.

the channel that received the SCA command);

having passed through a certain bus the group inputs-outputs 68-14 of the key block 4, forms a section limiting signal in the trunk;

0 pass element OR 51 through its third entrance to the key block 4 through its defined bus group inputs-outputs 68-14, forms in the trunk signal to prevent the capture;

The 5th pass of the OR 55 element on its second input opens the AND 47 element on its second input, thereby allowing the passage of signals from the output of the fifth element OR 52 through its first input.

0 the input of this element in the future will be received by serial code information signals on the corresponding bus from the second group of outputs of 64 key blocks 4.

5 In the initiating channel, the signal for limiting the section received from the corresponding bus of the second group of inputs-outputs 66 of the key block 5 passed through the elements AND 31 and OR 54 through their second and first

0 inputs, respectively, sets the state register 6 to the second position, in which potential 1, from its output, does the following:

closes the key block 4 at its control input;

having passed the OR 50 element through its second input enters the enabling input of the key block 5, thereby maintaining the open state of the group inputs / outputs

0 69-16.

Thus, the section of the trunk open for the exchange of information and control signals is limited to a key block 4 of the initiator channel and a block of the 5 key destination channel.

The fourth clock pulse, having passed the AND 34 element, cannot pass through the direct second input of the AND 45 element, since it is closed on the inverse input with a high potential coming from the third output of the state register through the OR element 55 at its second input.

Fifth clock pulse, pass element And 35, as well as OR 56 on its first

The 5th input, arrives at the synchronous input 82 of the transceiver 26, and having additionally passed the element OR 58 through its second input to the synchronous input of the register 63 of commands, resets it to its initial state on the falling edge. The leading edge of the pulse transmitted by the synchronous input 82 to transceiver 26 is entered through a group of information inputs 75 of information from the status register into it, and the falling edge in transceiver 26 starts the operation of issuing the state byte entered into it. This status byte from the information output of the serial code 77 of transceiver 26 passes the second amplifier 3 through its second input and through the output 12 of the channel enters the communication link with the initiator computer, informing about the execution of the PCA command.

Having received in response to the state byte command, the computer analyzes it, and, having made sure that the channels and the trunk are ready to exchange information with the subscriber, it starts the exchange.

Information byte parcels in the initiator channel from input 11 through amplifier 2, key block 5 through its defined information input-output bus 69-16, arrive at the destination channel, in which from the second group of outputs 64 key block 4 through OR elements 52, and 47 and amplifier 3, through their first inputs, pass to the communication line with the target computer. A similar way, but in the opposite direction, passes byte information parcels from the target computer: in the channel address through its input 11, amplifier 2, key block 4 through its group inputs-outputs 68-14, then along the open section of the trunk through the key block 5, via its group input-output 15-66, they enter the initiator channel, in which, through the OR element 52, through its second input, the AND element 47 and the amplifier 3 enter the communication line with the computer initiator.

In each intermediate channel located in the occupied section of the highway, the passing of foreign information after the element OR 52 is blocked by the element AND 47 at its second input, which is supplied with a low potential flowing through the element OR 55 from the second and third inputs of the state register b.

At the end of the dialogue between the subscribers, one of them sends a command to the CS channel, after receiving which by transceiver 26 and the last command unit 60 interacting with the first clock pulse, output code 0101 is set on the output buses of the command register 63 63. By potential 1 from the second output of the register 63 commands are opened elements AND 36-38 at their first entrances.

The second clock pulse passes the element I 36 through its second input, the key block 5 through its group input-output 69-16 and

then through the trunk to the destination channel, in which, as a signal to complete the communication, it will arrive from the second group of outputs 64 of the key block 4 through the element OR 57 through its fifth fourth input and will receive a reset

Register 6 states, transfer it to its original position. In the initiator channel the third clock pulse passed the elements AND 37, OR 57 through their second and first inputs

0, respectively, arrives at the reset input of state register 6 and returns it to the initial state. The fifth clock pulse, passing the elements 38 and OR 56 through their second inputs, enters the synchronous input 82 at 5 of the transceiver 26, and the additional element OR 58 passes through its second input, enters the synchronous input of the register 63 commands, resets it to its initial state back front. The front edge of the pulse passed through the synchronous input 82 to the transceiver 26 is entered into it through a group of information inputs 75 information from the state register, and the falling edge starts the transmission operation

5, by which from the information output of the serial code 77 of the transceiver 26, the status byte code is output through the amplifier 3 via its second input and the output 12 of the channel to the computer.

0 It should be noted that from the moment of establishing a connection between computers, the initiator and the addressee have meaning only from the point of view of the program organization of a dialogue. The channels of the device themselves become

5 equal, their difference is determined by the contents of the status registers: one has the second position, the other - the third.

In the case where the destination channel has a sequence number smaller than the initiator channel, the procedure for executing the SCA command is similar, therefore, the operation of the second decoder 29 and AND 31 can be disassembled using the example of decoder 28 and AND 30.

five

Consider the second situation in which the section of the trunk passing through the initiator channel is occupied by another pair of subscribers. In this case, the initiator channel of the status register 6 is in the initial position, and from the corresponding buses of the second groups of outputs 64 and 66 of the key blocks 4 and 5, respectively, the first and second inputs of the OR 48 element receive the potential

5 T signal of the prohibition of capture. The operation of the channel to establish communication between the subscribers of the system by the command of the PCA does not differ from that described above, up to the appearance of the code 0011 on the output buses of the command register 63.

Low potentials from the second and third outputs of the state register 6, having passed the element OR 55, close the element AND 43 at its second input and open the element AND 44 at its inverse input.

The high potential from the output of the element OR 48 closes And 41 in the inverse input and opens the element And 42 in the second input.

The second clock pulse, passing the elements AND 32.42 and 44 through their second, first and forward inputs, respectively, sets position 4 to state register 6. In this position, the low potentials from its first, second, and third outputs, passing through the elements OR 49, 50 to the enable inputs, respectively, of the key blocks 4 and 5, leave their third group information inputs 68 and 69 disabled. Therefore, the third clock pulse that passed through element 33 and the address code received from the second group of outputs 83 of transceiver 26 does not pass through group inputs 68 and 69 of key blocks 4 and 5, respectively, to the trunk, thereby eliminating interference in the system.

The fourth clock pulse, having passed the AND 34 element, is not passed by the AND element.

45, which in its first direct input is closed by a low potential coming from the first output of the state register 6.

The fifth clock pulse, as in the previous situation, passed the AND 35, OR 56 and 58 elements, enters the transceiver information from the state register, starts the transmitter, resets the command register 63 to the initial state. The difference is that the high potential from the fourth output of the state register, passed the element OR 59 through its first input, opened the element I 46 through its second input. Therefore, the fifth clock pulse from the output of the element 35 will also pass the elements AND

46, OR 57 in their first and third inputs, respectively, and their falling edge will reset the state register 6 to its original position.

Thus, the attempt to connect through the device with the target computer fails because of the busy line, which the initiator computer will know when analyzing the response byte of the state.

Consider the third situation where the section of the trunk passing through the initiator channel is free, but the destination channel is located on an inaccessible part of the trunk (or is engaged in dialogue with another subscriber, or is separated from the channel in question by a section captured by another pair

subscribers). In this situation, as in the first one, when the ZKA command is executed on the second and third clock pulses, the address and the address strobe signals are sent via the trunk, but since the subscriber is not found, the signal for limiting the section in the initiator channel is received by the time the fourth clock pulse arrives will not exist, and the state register 6 remains in the first position. The fourth clock pulse, pass element 34 and 34, as well as along the second direct input, element 45, which is open at the first direct input with high potential from the first output of register 6

The 5 state, and the inverse input-low potentials from the second and third outputs of the state register, passed through the element OR 55, puts the state register 6 in the fifth position. Potential 1 with his

0 of the fifth output, passed through the second input of the element OR 59 to the second input of the element A and 46, allows the signal to pass through the first input of the element AND 46.

With the fifth clock pulse, the execution of the SCA command is completed in the same way as in the second situation. A computer distinguishes situations by analyzing a status byte.

Consider the fourth situation in which, by the time the SCA command is executed

0 the channel in question is already occupied by a reciprocal call to it by a subscriber,

In this case, the status register 6 is in the second or third position, depending on the direction from which the channel is occupied, and the second group of exits 64 or 66 of the key blocks 4 or 5, respectively, receives the seizure inhibit signal from the trunk.

0 The operation of the channel in question when the SCA command is sent to it is similar to the process described in previous situations, up to the appearance of the code 63 on the output buses of the command register 63 code 0011.

five

Potential 1 from the second or third outputs of state register 6, having passed the element IL AND 55, opens element AND 43 at its second input. High signal potential

0 of the prohibition of capture, having passed the element OR 48, closes the element AND 41 on the inverse input and opens the element AND 42 at its second input.

The second clock pulse, passed through 5, therefore, elements AND 32 at the second input, and then elements AND 42, AND 43 and OR 58 at their first inputs, resets command register 63 to its original state, thus completing the execution of the PCA command.

Thus, preservation of the state register position and elimination of the state byte transmission prevents communication failure and distortion of information starting to come from the subscriber who first captured a part of the trunk and the channel in question. The computer in response to the sending of the command, the SCA will receive, instead of the expected confirming byte of the state, the first information byte from the reciprocal computer, in which, according to the protocol channel level of the exchange, there should be information about the start of the exchange initiated by a certain subscriber.

The channel operation when receiving the UCS command does not differ from the channel operation in case of receiving commands of the PCA and CS, but as a result of receiving commands in register 63, code 1001 is entered. Potential 1 from the third output of register 63 commands opens elements 39, 40 at their first inputs.

The second clock pulse, having passed successively the elements of AND 39 and OR 57 through their first and second inputs, respectively, resets state register 6 to the initial position. Fifth clock pulse, passed the element And 40 and the element OR 56 through their second and third inputs, respectively, completes the execution of the command of the UCS as well. like the teams of the cop. As a result, the channel is set to its original state, and in the state byte transmitted to the computer, this is reported.

A multichannel device for interfacing computers containing n channels, each of which contains two amplifiers, two key blocks and a status register, the first and second groups of information inputs and outputs of the i-ro channel (i 2, n-1) connected to the second groups of outputs and inputs (i-1) -ro of the channel and the first groups of information outputs and inputs of the 0 + 1) -th channel respectively, the information inputs and output of the serial code of the i-ro channel are the corresponding input and output devices for connecting to inform The output and input of the corresponding computer, each input of the first amplifier and the output of the second amplifier are respectively the information input and output of the serial channel code, the first groups of information inputs and outputs of the first and second key blocks are respectively the first and second groups of information inputs and channel outputs, characterized in that, in order to increase

the reliability of the device, a clock unit is entered into it, jBbixoA and j- group of outputs of which (J - 1, p) are connected respectively to the synchronization group and 5 clock inputs of the j-ro channel, and an asynchronous serial transceiver is inserted into each channel, block matching, consisting of two address decoders, eighteen AND elements and twelve

0 OR elements, and a command block consisting of a command decoder, a delay element and a command register, each channel having the first output of the status register connected to the first inputs of the first and second AND elements, the first inputs from the third to the sixth elements AND are connected to the first output of the command register, the second output connected to the first inputs from the seventh to ninth AND elements, and the third output to the first inputs of the tenth and eleventh AND elements, the group of outputs and the first information input of the command decoder are connected to responsibly with a group of information inputs

5 and the fourth output of the command register, the second inputs from the third to the eleventh And elements and the clock input of the command decoder form a group of channel clock inputs, the output of the third And element is connected to the direct input of the twelfth And element and the first input of the thirteenth And element, the output of which is connected to the first input of the fourteenth element I and the direct input of the fifteenth element I,

5, the output of the first element OR is connected to the second input of the thirteenth element AND and the inverse input of the twelfth element AND, the output connected to the first information input of the status register,

0 whose first output is connected to the first direct input of the sixteenth element AND and the first inputs from the second to fourth elements OR, the output of the sixth element AND is connected to the first input of the seventeenth

5 of the AND element, the output of the fifth OR element is connected to the first input of the eighteenth element AND, the first inputs of the sixth and seventh OR elements are connected respectively to the outputs of the first and second

0 elements And, and the second inputs - respectively with the outputs of the first and second address decoders, the first input of the second amplifier is connected to the output of the eighteenth element And, the second input of which is connected to the second input of the fourteenth and inverse inputs of the fifteenth and sixteenth elements And and the output of the eighth element OR, from the first to the third inputs of the ninth element OR are connected respectively to the outputs of the sixth, ninth and

the eleventh AND elements, the reset input of the status register is connected to the output of the tenth OR element, the first to the third inputs are respectively connected to the eighth, tenth and seventeenth elements AND, the synchronous input of the command register is connected to the output of the eleventh OR element, the first and second inputs of the respectively, to the outputs of the fourteenth element AND and the ninth element OR. the second input of the seventeenth AND element is connected to the output of the twelfth OR element, the second output of the status register is connected to the second inputs of the third and fourth OR elements, the control input of the first key block and the first input of the eighth OR element, the second input of which is connected to the third output of the status register , the second input of the second element OR. the third input of the fourth element OR and the control input of the second key block, the first and second inputs of the twelfth element OR are connected respectively to the fourth and fifth outputs of the state register, from the second to the fifth information inputs of which are connected respectively to the outputs of the seventh and the sixth elements OR, the fifteenth and sixteenth elements AND, the second direct input connected to the output of the fifth element AND, from the first to the fifth state register outputs are connected to the group of information inputs of the asynchronous one of a transceiver, information inputs of the serial code output and the first group of outputs of which are connected by the corresponding output of the first amplifier, the second input of the second amplifier and the group of information inputs of the command decoder, the second information input of which

connected to the ready output of the asynchronous serial transceiver and through the delay element to the synchronization input of the receiver of the asynchronous serial transceiver, the clock input of which is the synchronizing input of the channel, and the synchronous input is connected to the output of the ninth element OR, the second group of outputs of the first key block is connected to the group of information inputs and sync inputs of the first address decoder, the first inputs of the first and fifth OR elements, the second input of the first element AND, the fourth input d The second OR element and the second group of information inputs of the second key block, the second group of outputs of which are connected to the second group of information inputs of the first key block, the group of information inputs and the synchronous input of the second address decoder, the second inputs of the second element AND and the first and fifth elements OR and n to the input of the tenth element OR, the third group of information inputs and the enabling input of the first key block are connected to the second group of outputs of the asynchronous serial transceiver, the third output ohms of the fourth and seventh elements AND, the fourth element OR, the first amplifier and the output of the second element OR, the third group of information inputs and the enabling input of the second key block are connected respectively to the second group of outputs of the asynchronous serial transceiver, the second register output , the outputs of the first amplifier, the fourth and seventh elements AND, the fourth element OR, and the output of the third element OR.

O f

№ g.Z

FIG 4

Claims (1)

Claim A multi-channel device for interfacing computers, containing η channels, each of which contains two amplifiers, two blocks of keys and a status register, the first and second groups of information inputs and outputs of the i-ro channel (I = 2, p-1) connected respectively to to the second groups of outputs and inputs of the (I-1) channel and the first groups of information outputs and inputs of the (i + 1) -ro channel, the information input and output of the serial code of the i-ro channel are the corresponding input and output of the device for connecting to the information output and in an ode to the corresponding computer, and in each channel, the input of the first amplifier and the output of the second amplifier are respectively the information input and output of the channel serial code, the first groups of information inputs and outputs of the first and second key blocks are the first and second groups of channel information inputs and outputs, respectively the fact that, in order to increase the reliability of the device, a clock unit is introduced into it, the _output and the Jth group of outputs of which (J - 1, p) are connected respectively However, with a synchronizing and a group of clock inputs of the j-ro channel, asynchronous serial transceiver, a matching unit consisting of two address decoders, eighteen AND elements and twelve OR elements, and a command unit consisting of a command decoder, an element are introduced into each channel delays and the register of commands, and in each channel, the first output of the status register is connected to the first inputs of the first and second elements And, the first inputs from the third to sixth elements And are connected to the first output of the command register, the second the output connected to the first inputs from the seventh to ninth elements And, and the third output to the first inputs of the tenth and eleventh elements And, the group of outputs and the first information input of the command decoder are connected respectively to the group of information inputs and the fourth output of the command register, the second inputs from the third eleventh elements And and the clock input of the command decoder form a group of clock channel inputs, the output of the third element And is connected to the direct input of the twelfth element And and the first input of the thirteenth element And, whose output is connected to the first input of the fourteenth element And and the direct input of the fifteenth element And, the output of the first element OR is connected to the second input of the thirteenth element And and the inverse input of the twelfth element And, the output connected to the first information input of the status register, the first output of which is connected with the first direct input of the sixteenth element And and the first inputs from the second to fourth elements OR, the output of the sixth element And is connected to the first input of the seventeenth element And, the output of the fifth element This OR is connected to the first input of the eighteenth AND element, the first inputs of the sixth and seventh OR elements are connected respectively to the outputs of the first and second AND elements, and the second inputs are respectively to the outputs of the first and second address decoders, the first input of the second amplifier is connected to the output of the eighteenth AND element , the second input of which is connected to the second input of the fourteenth and inverse inputs of the fifteenth and sixteenth elements AND and the output of the eighth element OR, from the first to the third inputs of the ninth element OR are not connected respectively with the outputs of the sixth, ninth and eleventh AND elements, the reset input of the status register is connected to the output of the tenth OR element, with the first through third inputs respectively connected to the outputs of the eighth, tenth and seventeenth AND elements, the clock register of the instruction register is connected to the output of the eleventh OR element, the first and second inputs connected respectively to the outputs of the fourteenth AND element and the ninth OR element. the second input of the seventeenth AND element is connected to the output of the twelfth OR element, the second output of the status register is connected to the second inputs of the third and fourth OR elements, controlling the input of the first key block and the first input of the eighth OR element, the second input of which is connected to the third output of the status register, the second input the second OR element, the third input of the fourth OR element and the control input of the second block of keys, the first and · second inputs of the twelfth · OR element are connected respectively to the fourth and fifth status register moves from the second to fifth invariant: formational whose inputs are connected respectively to the outputs of the sixth and seventh element or elements of the fifteenth and sixteenth And, a second input connected to the direct output of the fifth element:. And, from the first to the fifth outputs of the status register are connected to the group of information inputs of the asynchronous serial transceiver, the information inputs are the output of the serial code and the first: the group of outputs of which are connected corresponding to the output of the first amplifier, the second input of the second amplifier and the group of information inputs of the command decoder, Figure 1 is single with the availability output of the asynchronous serial transceiver and through the delay element with the synchronization input of the receiver of the asynchronous serial transceiver, the clock input of which is the channel synchronizing input, and the clock input is connected to the output of the ninth OR element, the second group of outputs of the first key block is connected to the group of information inputs and sync inputs of the first address decoder, the first inputs of the first and fifth elements OR, the second input of the first element AND, the fourth input of the tenth OR element and the second group of information inputs of the second key block, the second group of outputs of which is connected to the second group of information inputs of the first key block, the group of information inputs and the clock input of the second address decoder, the second inputs of the second AND element and the first and fifth OR elements and the fifth input of the tenth OR element, the third group of information inputs and the enable input of the first block of keys are connected to the second group of outputs of the asynchronous serial transceiver, the third output the status register and the outputs of the fourth and seventh AND elements, the fourth OR element, the first amplifier and with the output of the second OR element, the third group of information inputs and the enabling input of the second key block are connected respectively to the second group of outputs of the asynchronous serial transceiver, the second state register output, the outputs of the first amplifier, the fourth and seventh elements AND, the fourth element OR and the output of the third