SU1109909A1 - Checking device - Google Patents

Abstract

CONTROL DEVICE containing the first input bus, counter, multiplexer, delay element, first element NOT, first trigger and first element AND, the first and second inputs of which are connected respectively to the output of the first element NOT and to the output of the delay element whose inputs are connected to the output of the multiplexer The control and information inputs of which are connected respectively to the control buses and to the outputs of the counter, the addition input of which is connected to the first input bus, characterized in that, in order to expand the function the second input, the second and third elements AND, the element OR, the element OR NOT, the second and third elements NOT and the second trigger, the installation input in which is connected to the installation input in. About the first trigger and with the output of the OR element, the first and second inputs of which are connected respectively to the first inputs of the second and third elements AND and connected respectively to the outputs of the second and third elements NOT, the inputs of which are connected respectively to the first and second input buses, the last of which connected to the subtraction input of the account (Tacho, the inputs of the OR-NOT element are connected respectively to the output of the first element NOT and to the output of the delay element, the outputs of the first AND element, the OR-NOT element are connected respectively with the second inputs of the second and third AND gates, which are connected vkody sootvet1G 4 It governmental with setting inputs u;. of the first and second flip-flops with a

Description

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The invention of the computation to the lagoon technique can be used to control the reversing counter to reach a given code state in digital measurement and computing systems, in particular when building

reversible counters with controllable conversion factor.

A control device is known comprising a counter, a multiplexer, a trigger, an inverter, and a match element 1 1.

The disadvantage of the device is relatively low control accuracy,

It is also known a control device comprising an input bus, a counter, a multiplexer, a delay element, a NOT element, a trigger, and an AND element whose first and second inputs are connected respectively to the output of the HE element and to the output of the delay element, the inputs of which are connected to the output of the multiplexer, control and information inputs of which are connected respectively to the control buses and to the outputs of the counter, the input of which is connected to the input bus and to the input of the installation in 1, a trigger, the input of the installation in which is connected to the output of the element NTA and 2}

A disadvantage of the known devices is the limitation of its functionality.

The purpose of the invention is to expand the functional capabilities of the control device due to the possibility of accurately determining whether zero moments or a unit of output signals of a predetermined number of bits of the reversible counter in the forward and reverse counting modes, respectively.

To achieve this goal, the control device containing the first input bus, counter, multiplexer, delay element, first element NOT, first trigger and first element AND, the first and second inputs of which are connected respectively to the output of the first element NOT and to the output of the delay element inputs which are connected to the output of the multiplexer, the control and informational inputs of which are connected respectively to the control buses and to the outputs of the counter, the addition input

PPD91

KOToiHirc) is connected to iiepFioii by iijHiioii nkhodpoy, pps / nyyyyyy input bus, second and TpcTini elements AND, element RlH, zlgmont And, 1I-NK, second and three, Tiifi-part III and second tripper, installation in About which connected with the input of the installation in O of the first Trigger, and with the output of the H, the gement OR, whichever and the second inputs of which co) Q are united, respectively. The first inputs of the second and third elements are And and are connected respectively to; the inputs of the second and third elements HR, the inputs of which are connected respectively to the first and second input buses, the last of which is connected to the subtraction input of the counter, the inputs of the element OR NOT are connected respectively to the output of the first element is NOT and with the output of the delay element, the outputs of the first element AND and the element OR are NOT connected respectively to the second inputs of the second and third elements AND outputs ko2. They are connected respectively with the installation inputs in 1 of the first and second triggers.

FIG. 1 shows a structural diagram of the proposed device k.ont, ROLE; in fig. 2 and 3 are the time diagrams of the device operation in the forward and reverse counting modes, respectively.

The device contains a multiplexer 1, the first element is NOT 2, the element 3 is a delay, the first element is AND 4, the first trigger 5, the counter 6, the first input bus 7, the control bus 8, the second input bus 9, the element OR NOT 10, the second and third elements And 11 and 12 respectively, the second and third elements are NOT 13 and 14, respectively, the element OR 15 and the second trigger 16.

The first input bus 7 and the second input bus 9 are connected respectively to the addition and subtraction inputs of the counter bis inputs of the second element HE 13 and the third element NOT 14, the outputs of which are connected respectively to the first inputs of the second element 11 and the third element 12 and to the first and second the inputs of the element OR 15, the output of which is connected to the inputs of the installation O of the first trigger 5 and the second trigger 16, the inputs of the installation in 1 of which are connected respectively to the outputs of the second element 11 and the third element 12, the second inputs of which are connected respectively, with the outputs of the first element AND 4 and the element OR-NOT 10, the first inputs of which are connected to the outputs of the first element NOT 2, the second inputs of the first element AND and the element OR-NOT 10 with the output of the delay element 3, the input of which is connected to the input of the first element NOT 2 and with the output of multiplexer 1, the information and control inputs of which are connected, respectively, with the outputs of counter 6 and with control buses 8. FIG. 2 shows timing diagrams 17-25 of signals, respectively, on bus 7, from the outputs of the first and second bits of counter 6, at the output of the multiplexer with the control code on buses 8, which provide the switching of the second input of multiplexer 1, at the output of the HE element 2, at the output of the element delay, at the output of the element And 4 and at the output of the trigger 5. In FIG. 3 shows timing diagrams 26-34 of signals, respectively, on bus 9, from the outputs of the first second and third bits of counter 6, at the output of multiplexer 1 with the control code on buses 8, providing switching of the second input of multiplexer 1, at the output of the HE element 2, at the output of the element 3 delay, at the output of the element OR NOT 10 and at the output of the trigger 16. The device works as follows. Depending on the code at the control inputs of multiplexer 1, a signal from the output of one of the bits of the controlled counter 6 passes at its output, which is the most significant bit of the controlled ones. In the direct counting mode, the counting pulses go to bus 7, while bus 9 is supplied with logic level 1. When the controlled bits of counter 6 are in one state, a single logic signal is present at the output of the multiplexer. With the arrival of the next counting pulse the absence of the corresponding bits of the controlled counter 6 takes place from single logic signals to zero. The corresponding differential of the logical signal also appears at the output of multiplexer 1, with the most significant bit of the controlled counter 6 going from a single logical state to zero when all the least significant bits in relation to it also go from a single state to zero. The zero logical signal from the output of multiplexer 1 is fed to the first input of the AND 4 element through the HE 2 element, and to the second input through the 3 delay element. As a result, in the moment of switching the output signal of multiplexer 1 at the inputs of element 4, there are signals of logic 1, and at its output a pulse is formulated, the duration of which is determined by the amount of delay specified by element 3 of delay. The formulated pulse from the output of the element 4 through the open element 11 is fed to the input of the installation in 1 of the trigger 5 and switches this trigger, from the output of which a signal is taken indicating that the controlled bits of the counter are in the zero state. The trigger 5 is returned to its original state by a pulse formed from the next counting pulse by the elements 13-15, which enter the input to the O of the trigger 5 when the zero of the monitored output code is violated. In the direct counting mode, the pulses generated by the OR-NOT 10 element are not passed by the AND 12 element, which is closed by the zero level present at its second input, the NOT 14 element formed from the unit level present on the 9-line direct counting mode. Meanwhile, the trigger 16 cannot switch and is in the zero state. In the countdown mode, the counting pulses are sent to bus 9, while bus 7 is supplied with logic level 1. When the monitored charges of counter 6 are in the zero state, a zero logic signal is present at the output of the multiplexer. With the arrival of the next counting pulse at the output of the corresponding bits of the monitored tester 6, the transition from the Nue logic signals to the unit ones takes place. The corresponding differential of logical signals also appears at the output of multiplexer 1, with the most significant bit of the controlled counter 6 going from zero to one when all the least significant bits in relation to it also go from zero to one. A single signal from the output of the type 1 multiplexer is fed to the first input of the element OR NOT 10 through the element NOT 2, and to the second input through the element 3 delay. As a result, at the moment of switching to the (go-on signal of multiplexer 1, the inputs of the OR-NOT 10 element contain zero logic signals, and a single pulse is formed at its output, the duration of which is determined by the amount of delay specified by delay element 3 NOT 10 through the element I 12 opened in this 1 oment arrives at a single input of trigger 16 and switches this trigger from which output a signal is taken indicating 96 that the counters of the counter are controlled in the reverse mode. The trigger 16 returns to its initial state with a pulse formed from the next counting pulse by elements 13-15, arriving at the zero input of the trigger 16, when equality to the unit of the controlled output code is violated. In the countdown mode, the pulses generated by the element And 4 is not passed by the element to; 1, which is closed by the zero level, is present at its second input, formed by the element NOT 13 from the single level present on bus 7 in the countdown mode. In this case, the trigger 5 cannot switch and be in the zero state. Thus, the proposed control device makes it possible to accurately determine whether the zero or unit of output signals of a given number of bits of the reversible counter, respectively, in the forward and reverse counting modes.

SG

13

one

No

ff

Claims (1)

CONTROL DEVICE containing the first input bus, counter, multiplexer, delay element, first element NOT, first trigger and first element AND, the first and second inputs of which are connected respectively to the output of the first element NOT and to the output of the delay element, the inputs of which are connected to the output of the multiplexer , the control and information inputs of which are connected respectively to the control buses and to the outputs of the counter, the addition of which is connected to the first input bus, characterized in that, in order to expand the functional opportunities, the second input bus, the second and third elements AND, the OR element, the OR-NOT element, the second and third elements NOT and the second trigger, the input of which is set to 0 is connected to the installation input to O of the first trigger and to the output of the OR element , the first and second inputs of which are connected respectively to the first inputs of the second and third elements AND and are connected respectively to the outputs of the second and third elements NOT, the inputs of which are connected respectively to the first and second input buses, the last of which is connected to the input reading the counter, the inputs of the OR-HE element are connected respectively to the output of the first element NOT and to the output of the delay element, the outputs of the first AND element, the OR-HE element are connected respectively to the second inputs of the second and third AND elements, the outputs of which are connected respectively to the inputs of the installation 1 of the first and second triggers. 606,601 g ns>