SU1307556A1 - Pulse duration generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in control systems for a pulse shaper of controlled duration. The purpose of the invention is to improve accuracy. To achieve this goal, a shaper 6 pulses, a delay element 11, a register 9, a comparison element 10 are entered into the device. The device also contains a trigger 1, a counter 2 pulses, input bus 3, the element OR 4, the element And 5, the output bus 7, the generator 8 clock pulses. I il. cl

Description

The invention relates to a pulse technique and can be used in control systems for a pulse shaper of controlled duration.

The aim of the invention is to improve the accuracy.

The drawing shows the functional diagram of the pulse width driver.

The shaper contains a trigger 1, a pulse counter 2, input buses 3, an OR 4 element, an AND 5 element, a pulse shaper 6 on the leading and falling edges of the pulse, an output bus 7, a clock generator 8, a register 9, a comparison element 10, a delay element 11 , the installation inputs of the counter 2 are connected to the input buses 3, and the outputs of the bits of the counter 2 through the element OR 4 are connected to the output bus 7 and the input of the former 6 along the leading and trailing edge of the pulse, the output along the leading edge of the former 6 is connected to the C input of the trigger 1 rear exit the front of the imager 6 is connected to the R input of the trigger 1, the single output of the trigger 1 is connected to the first input of the AND element 5, the second input of which is connected to the output of the comparison element 10, and the output of the AND element 5 is connected to the subtractor 11 delays are connected to the first and subsequent inputs of the first group of inputs of the comparison element 10 and to the D inputs of the first and next, their register bits 9, to the outputs of the driver 6, the outputs of zero, first and subsequent bits of the register 9 are connected to zero, first and subsequent moves the second element group 10 comparing inputs, the output of the generator 8 is connected to the input of the delay element 11, D-zero entry discharge register 9 and the zero input of the first band member 10 comparing inputs.

The number of input busbars 3 is determined by the code width specifying the duration of the generated pulse. The number of register bits 9 is equal to the number of inputs in the first and second groups of inputs of the comparison element 10 and one more than the number of outputs of the 1 1 delay element. The total delay time on the delay element 11 is equal to the duration of the period of the clock pulses of the generator 8.

As a generator of 6 pulses on the leading and trailing edge, one can use differentiating circuits with an inverter.

The shaper works as follows.

When inputting the input buses 3 into the counter 2, the code of a certain number K (, 2, 3 ...) corresponding to the specified output pulse duration at the output of the element 5, a signal appears on the output bus 7 and at the input of the imaging unit 6. In the moment

When the signal arrives, the driver 6 at its output on the leading edge generates a pulse that goes to the C input of the trigger 1 and to the inputs of the register 9 and the comparison element 10. The trigger 1 is set to a single state on the falling edge of the incoming pulse and opens element 5 on the first input. By the START signal from the imaging unit 6, the output of the comparison element 10 to the second input of the element 5 starts

receive clock pulses with the frequency of the clock pulses of the generator 8. Pulses from the output of the element And 5 subtract the contents of counter 2. When zeroing the counter 2 at the output of the associated element OR 4

signal ends. The shaper 6, at the end of the input signal, generates a pulse at the output of the trailing edge, which sets the trigger 1, the register 9 and the reference element 10 to the initial state.

0 Clock pulses from the output of the generator 8 are fed to the input of the element 11 of the delay, and, advancing on it successively, are fed to its outputs. The input and outputs of delay element 11 are connected to the D inputs of register 9, but writing to register 9 is not made until a START pulse arrives at its C outputs from the driver 6, and therefore register 9 remembers which output of element 11 There is a high potential in the delay at the moment of arrival of the pulse. a high potential appears at the output of the corresponding discharge. The comparison element 10, when the potentials at the outputs of the register 9 and the delay element 11 coincide, generates a pulse, which is fed to the input of the element 5.

The repetition frequency of these pulses is equal to the frequency of the generator 8 and shifted with respect to it by the shift of the start pulse relative to the pulse of the generator 8. When a reset pulse arrives from the former 6, the register 9 is zeroed and the comparison element 10 generates pulses coinciding in time with the clock pulses generator 8, i.e. At the output of the comparison element 10, sync pulses are formed that are equal in frequency to the input clock pulses and shifted by the magnitude of the synchronization of the start pulse and the generator pulse 8.

When the next code arrives at the input terminals 3, the described process is repeated.

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Claims (1)

Invention Formula A pulse width generator comprising a clock pulse generator, a pulse counter whose outputs are connected to the inputs of the multi-input element 55 OR, a trigger whose direct output is connected to the first input of the AND element, characterized in that, in order to improve the accuracy, a shaper and .m pulses on the leading and trailing edges of the im- and R-inputs of the register, respectively, pulse, delay element, register and output elements of which are connected to the first group, the output of which is connected to the second input of the comparison element, the second group input of the AND element, the output of which of the inputs of which is connected to the D-BXO is connected to the subtracting input of the counter, register ladies, and the output generator pulses, the output of the multi-input elementary pulses is connected to the first inlet or connected to the input of the former of the second group of inputs of the element of the comparative impulses along the front and rear edges and to the input of the delay element, the first and second outputs of which are connected to the D inputs, except connected to the C-and R-inputs of the trigger inulevogo register.