SU1376258A1 - Apparatus for block-wise timing of digital transmission system - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital transmission systems using multi-level block balance codes with redundancy. The purpose of the invention is to increase noise immunity of block synchronization. The signals of the ternary linear code through the shift register 1 and the key block 2 arrive at the detector 3 forbidden code words. When a forbidden code word is detected, the detector 3 generates a pulse that arrives at integrator 4. When the voltage of integrator 4 exceeds a certain threshold, threshold comparison unit 5 generates a pulse that resets integrator 4 through the element OR 13, and in frequency divider 6 by four the signal of a logical unit is transferred to another bit. Frequency dividers 6.7 into four, elements AND 8-11, OR 12 provide for setting the initial phase of the clock signal at the initial time of synchronization. The counter 14 of the number of analyzed code words sets the time interval. 2 Il.

Description

oh

ABOUT)

tsD

SP 00

The invention relates to telecommunications, and can be used in digital transmission systems using multi-level block balanced codes with redundancy.

The purpose of the invention is to improve the noise immunity of the block synchronization of the SRB.

FIG. Figure 1 shows the electrical block diagram of a device for block synchronization of a digital transmission system; in fig. 2 - timing diagrams for the operation of the device.

The device for block synchronization of the digital transmission system contains a shift register 1, a key block 2, a detector of 3 forbidden code words, an integrator, a comparison threshold block 5, first and second dividers 6 and 7 frequencies into four, first, second third and fourth elements AND 8 - 11, the first and second elements OR 12 and 13 and the counter 14 of the number of analyzed code words.

A device for block synchronization of a digital transmission system operates as follows.

The received signals of the ternary linear code (Fig. 2a) with a clock frequency (Fig. 2e) through the register 1 arrive at the corresponding inputs of the key block 2, from the outputs of which

the signals arrive at the corresponding inputs of the detector 3. The signal arriving at the control input of the key block 2 sets the initial phase (Fig. 26) of the block synchronization signal. Detector 3 searches for the forbidden code words. When a forbidden code word is detected, a pulse is generated at the output of the detector 3 (Fig. 26). The order of operation of the detector 3 is determined by the code table of the code used. From the output of the detector 3, the pulses come from the integrator 4 (Fig. 2c), to the control input of which from the output of the second element OR 13 pulses arrive, which set the integrator 4 to the initial state. From the output of the integrator 4, the signal is fed to the input of the threshold unit 5, in which it is compared with the threshold voltage Up (Fig. 2c). In the case when threshold U is exceeded, a pulse is formed at the output of threshold block 5 (Fig. 2d), which strikes the first input of the second element

ten

15

, five

20

thirty

35

45

40 g

0

RSHI 13 and to the input of the first divider 6 frequency. When a pulse frequency (Fig. 2d) arrives at the input of the first divider 6, the signal of the logical unit goes into the second discharge (Fig. 2L), and the outputs of the remaining bits are set to the zero state (Fig. 2k, m, and n) and t. .d At the same time, the clock frequency signals (Fig. 2d) are fed to the input of the second frequency divider 7. When a second signal of the logical unit (Fig. 2e) arrives at the input of the second divider 7, the pulse appears only at the output of the first bit (Fig. 2e). Each subsequent pulse arriving at the input of the second frequency divider 7 causes the output signal to transition to the next bit (Fig. 2g, 3, and 2).

Thus, at the initial time of synchronization, the joint operation of the first and second dividers 6 and 7 of the frequency, the first, second, third and fourth elements AND 8-11 and the first element OR 12 ensures that the initial phase of the clock signal is set (Fig. 2o). At the same time, in integrator 4, a count of a predetermined number of forbidden code words begins, and in counter 14, a predetermined interval of N code words begins. The time interval T, determined by the number of analyzed code words N, depends on the time to be entered into synchronism by setting counter 14 to the counting mode to N.

Claims (1)

Invention Formula A device for block synchronization of a digital transmission system, comprising a shift register, a series of forbidden code words connected in series, an integrator, a comparison threshold unit and a first frequency divider, which outputs are connected to the first inputs. the first, second, third and fourth elements And, to the second inputs of which the corresponding outputs of the second frequency divider are connected to four, the outputs of the first, second, third and fourth elements And are connected to the corresponding inputs of the first element OR, the counter of the number of analyzed code words, the clock input of the register shear combined with the input of the second frequency divider by four and is a clock input of the device, characterized in that, in order to improve the block synchronization immunity, a key block and a second OR element are entered, while the outputs of the threshold comparison block and the counter of the number of analyzed code words are connected respectively to the first and second inputs of the second element OR, the output which is connected to the control inputs of the integrator and the counter of the number of analyzed code words, and the outputs of the shift register are connected to the corresponding inputs of the prohibited code words detector via a key block, to the control input of which and the counter of the number of analyzed code words are connected which is the output of the device.