SU661809A1 - N-digit binary counter checking device - Google Patents

Description

The invention relates to computing.

Known binary counter with built-in control, containing two diode assemblies, two elements And two control trigger and the element OR 1.

A disadvantage of this device is the complexity of constructing a control circuit due to the fact that circuits are used using an additional source of reset pulses, namely, in the installation of meter triggers and control triggers in the state "O and" 1, in addition, the device availability time is reduced by checking the counter in a static state.

It is also known a device for controlling the operation of a counter with potential outputs, containing two AND elements, two dividers by 2 and an OR element 2.

This device has sufficient speed, but it only partially detects failures in the counter.

The closest to the technical essence of the present invention is a device for monitoring the n-bit binary counter, containing two elements And, n inputs of the first of which

are connected, respectively, with the direct outputs of the bits of the counter, and those of the second, with the inverse outputs of the bits of the counter, and the delay element 3.

However, this device doesn’t detect malfunctions when the counter is operating during the pulse counting process, which limits the field of application of this device.

The purpose of the invention is to extend the functionality by detecting device failures.

The goal is achieved by the fact that the device for controlling the "-disable binary counter, containing two elements AND, the inputs of the first of which are connected, respectively, in the direct outputs of the discharge bits of the counter, and the inputs of the second-- with the inverse outputs of the bits the counter and the delay element are entered a three-bit frequency divider and the element I, and the input of the controlled counter is connected to the input of the three-bit frequency divider, the outputs of the bits of which are connected, respectively, to the inputs of the third, element And, the additional input connected to the output of the first AND gate and the output of the third AND element is connected via a delay element with n + 1 input of the second element I.

FIG. 1 shows a functional diagram of the device; in fig. 2, 3 work diagrams.

The device contains a frequency divider 1, a controlled binary counter 2 consisting of binary cells 3, the elements 4-6 and the delay element 7, the input bus 8 and the output bus 9.

The device works as follows.

When the signal is reset, the binary cells 3 of the counter 2 and the three-bit divider of the first frequency are reset to their original zero state.

In the case of the correct operation of the controlled counter 2, when counting pulses are applied to the bus 8, a number corresponding to the binary number 1111 ... 1 is established in a binary cell 3 of a counter 2 after a certain period of time. From the right outputs of binary cells 3 (Fig. 2, output 3 a) high potentials arrive at the input of element i 5, at the output of which, in the case of coincidence of signals at the input, we receive a pulse (fig. 2, output 5), which arrives at one input of the element i 4, and the other inputs of this element receive high potentials from the main outputs of a threefold one frequency divider 1 and in the case of coincidence of the signals at the input, from the output of the AND 4 element (Fig. 2, OUT.4), we get a pulse triggering the delay element 7 (Fig. 2, output 7).

Further, in the counting process, when the next pulse arrives, on the right outputs of binary cells 3 of counter 2 a number m is set, corresponding to the binary number 000 ... O, and on the left outputs of binary cells 3 of counter 2 a number k is set inverse to the number on the right outputs, i.e., the binary number 11II ... 1 (Fig. 2, output 3), thus, high potentials arrive at the inputs of the AND 6 element, to the other input of which a pulse arrives from the delay element 7 delayed by time equal to the change in the counter 2 from the direct p to the inverse m and ave and the coincidence of the signals from the output 9 of the element. V6 an impulse for the correct operation of the monitored counter is output (Fig. 2, Ex. 9).

Thus, when the signals taken from the direct and inverse outputs of binary cells 2, as well as the signals from the outputs of the AND 5, AND 4 elements and delay element 7, are in the zone of the meter in good operation, the output device receives a pulse the operation of the monitored counter while monitoring the correct operation of the counter is performed between two duty cycles at the end of one and the beginning of the other.

In the event of a malfunction in the operation of at least one of the binary cells 3 of counter 2, the output of the device does not have a pulse of proper operation.

In the event of a failure, for example, a binary cell of the second bit, on the right output of which a high potential is established all the time, and despite the fact that 5 elements 5 and 4 and 7 delay elements 7 work, element 6 does not work due to low potential at the other output of the binary cell of the second bit.

Thus, at the exit of the 9th element

Q & 6 is no impulse for proper operation. In the case of failure of a binary cell of the second bit, when a low potential is set at all times for the right output, then in the 3foM case the elements AND 5, AND 4 and the delay element 7 do not work, since

5, the coincidence signals at the inputs of the And 5 And 4 elements are absent, therefore, the potential of the delay element 7 is low, so that at the output 9 of the And element 6 there is no operational pulse. The case is considered when the outputs of binary cells 3 of counter 2 have normal combinations of output levels, but one of the binary cells does not work out all the input signals, for example, the first-stage binary cell did not respond to one of the input signals (Fig. 3, output 3 , 3)

In this case, the And 5 element is triggered (Fig. 3, Out. 5), but the And 4 element does not work as there is a low level signal on one of the inputs, therefore, from the output

0 of the element AND 4 also has a low level signal (Fig. 3, output 4), thus, delay element 7 does not work either (Fig. 3, output 7), therefore, from the output of the element 6 working impulse

5 is absent for the entire duration of the count, despite the fact that a single failure has occurred.

The control of the counter operation in the interval between the counting pulses is based on the fact that no false positives of one of the binary cells 3 of the counter 2 should

be.

In the event of a failure, for example, if one of the binary cells of the counter malfunctions when a penetration of a fur, for example, along power supply lines, is output, a signal of correct operation is missing at the device output.

Thus, the absence of a signal in the zone of correct operation of the counter of at least one of the pulse sequence leads to the absence, at output 9, of the element AND 6

impulse of correct operation of the counter.

The proposed device is characterized by high reliability and reliability of control both in case of sudden failures of one or several binary counter cells, and in the case when the binary counter cells have normal combinations of output levels, but not all input signals are working, i.e. when a failure occurs .

Claims (3)

1. USSR author's certificate number 463113, cl. G 06 F 11/00, 1975. 2. USSR author's certificate number 416883, cl. H 03 K 21/34, 1974. 3. USSR author's certificate No. 219896, class, G 06 F 11/00, 1968.  P P P P P P P P P P P P P P P P P P P P P P R P zh.z nnnnnnjzihnnnnnnf .З. awxj . VykZ Vyh.E. vsh.z Vm. Vsh.z. vy.z & t. 1 out 1 St / K.I off 5BbK .lt By%% .7-. 8OUT .g