SU378875A1 - ALL-UNION ?: I - Google Patents

Description

one

The invention relates to computing and can be used, in particular, as part of specialized computing devices for processing hydrophysical information (for example, when calculating the dispersion and spectral density function of hydrophysical processes). However, analog devices have high methodological error, are cumbersome and have strict requirements for the elements used in them, and digital devices are complex and have low reliability.

The aim of the invention is to simplify the device and increase its reliability.

This goal is achieved in that the device additionally contains drivers and delay lines. The output of the clock generator through the first trigger, the driver and the counter-divider is connected to the first input of the first circuit. And through the first delay line connected to the first input of the inhibitor circuit and through the comparison circuit connected to the second input of the prohibition circuit. The second input of the comparison circuit is connected. to the terminal of the numeric input, the zero output of the second trigger through the second driver is connected to the second input of the first trigger and through the second delay line is connected to the single input of the second trigger and to the terminal set Nogo input, single output

the second trigger through the second circuit "And the counter-drive is connected to the second input of the first circuit" And the output of which is connected to the output terminal of the device, the output 5 of the first driver is connected to the second input of the second circuit "I.

The proposed device allows the square of the original number to be calculated with a given accuracy in real time. It

0 reliably and can be used both autonomously and as a template for a digital computer. The information is input and output in digital form, which makes it easy to dock the proposed device with a digital computer.

5 The drawing shows a functional diagram of the proposed device.

The main nodes of the quad are: the numeric input / (it is numerically supplied with the number a, which must be erected

0 squared); sensor 2 of random numbers with a comparison circuit (the block is used to generate uniformly distributed random numbers Ri at the clock points of time and compare it with the initial number a at the output of block 2

5, the output signal appears if the condition is satisfied); 3 clock pulse generator (GTI); trigger 4 with separate input; installation input 5; trigger 6 with a counting input; counter drive 7; counter 0 divider S; shapers 9 to 10 with a delay; ban scheme 11; delay lines 12 and 13; schemes 14, 15 "I.

Quad works as follows. Using setpoint input 5, trigger 4 is set to one state, and trigger 6 is set to zero. The numeric .INIT / is supplied with the number a, which must be squared. When a clock pulse is applied from the GTI 5 in block 2, a uniformly distributed random number Ri is generated and compared with the initial number a. When fulfilled in block 2 of condition Ri, a signal appears at its output, which arrives on a "prohibition" circuit. At the same time, a delayed clock pulse is transmitted to the second input of the inhibit circuit, which is passed through the delay line 12 (the delay time is determined by the inertia of the unit 2), which tends to reset trigger 4 to the zero state. Since the output signal of block 2 supports the inhibit circuit in the closed state, the clock pulse does not pass the inhibit circuit, and trigger 4 remains in the unit state. At the same time, the clock impulse arrives at the counting input of the trigger 6 and transfers it to a single state.

The proposed quad works on the principle of statistical tests and counting the total and positive number of tests. A positive test for building the initial number into a square is that the condition in block 2 is twice the order. One test is considered to be twice the supply of a clock pulse to input 3.

If the condition is fulfilled in block 2 twice a second, then the output signal from the single output of the trigger 6 passes the delay shaper 9 and the open gate 14 of the polling of the trigger 4 (since the trigger 4 remains in the unit state) and fixes the unit in the counter 7. At the same time registers the test in the counter 8.

If condition Ri a is not fulfilled in block 2 a second time, then the delayed clock pulse passes the inhibit n circuit resetting trigger 4 to the zero state. In this case, the output trigger signal 6 passes the driver 9 and fixes the test in the counter 8. This signal does not pass through the interrogation gate 14, since the trigger 4 at the time of the interrogation turned out to be in the zero state. The delay time in the driver 9 is selected so that the trigger 4 has set to the zero state before the output signal of the trigger 6 arrives at the gate 14. The flip signal from the zero output of the trigger 4 passes through the driver with a delay of 10 and through

delay line 13 and sets trigger 4 to the next test. The delay time in the driver 10 is selected such that the trigger 4 returns to the one state after the signal from the driver 9 comes to the closed poll gate 14.

If the condition is not fulfilled in block 2 for the first time, then the second test

there is no need to conduct it. In this case, the output signal of the trigger 4 through the driver 10 sets the trigger 6 to the zero state and, via the delay line 13, sets the trigger 4 to the state one. The delay time on line 13 is chosen longer than the delay time in driver 9 in order for trigger 4 to remain in the zero state when the output signal for switching trigger 6 is outputted to valve 14.

The described test sequence is repeated several times until counter 8 overflows, the output of which opens a group of decommissioning valves 15, and from the output of counter 7, where the result accumulates

The calculations are written off a number that is an approximate value of the square of the input number.

Subject invention

A quadrator containing a comparison circuit, a counter-accumulator, a counter-divider, a inhibitor circuit, triggers, a clock generator and an AND circuit, characterized in that, in order to simplify the device, it further comprises drivers and delay lines, and the clock pulse output through the first trigger, the first driver and the counter-divider is connected to the first input of the first circuit "And, through the first delay line is connected to the first input of the inhibit circuit and through the comparison circuit is connected to the second input of the prohibition circuit,

the second input of the comparison circuit is connected to the terminal of the numeric input, the zero output of the second trigger through the second driver is connected to the second input of the first trigger and connected via the second delay line

with a single input of the second trigger and with a terminal of the installation input, a single output of the second trigger through the second And circuit and a storage drive connected to the second input of the first And circuit, the output of which is connected to the output terminal of the device, the output of the first driver "AND.