SU378850A1 - DEVICE FOR CONTROL OF DIGITAL COMPUTING MACHINE '^ ^^ i.'v.'UiiJdHAyry-gt-mt ^^ ЕШ - Google Patents

Description

The invention relates to digital computing and can be used in software-controlled digital computers.

A device for controlling a digital computer is known, consisting of a command counter, an operation control device, an error handling device, a failure signal generation unit, a return circuit by tags, a tag generation and storage unit, an error analysis unit (failure detection), a failure counter. .

The aim of the invention is to increase the reliability of the separation of long-term failures from failures, increase the operation, reliability of the digital computer and the formation of data on the duration of the failures.

This is achieved by the fact that the device additionally contains a fault duration counter, a start unit and read valves. The counting input of the fault duration counter is connected to the output of the start block, whose input is connected to the output of the error detection device, the second input of the start block is connected to the main pulse bus, the third input of the start block is connected to the output of the operation control device, the overflow exit of the fault duration counter is connected to the input of the digital signal generation unit for the failure of the digital computer; the information output of the fault duration counter is connected to the inputs of the read valves, the second inputs of which are connected to the outputs of the operative control device atsi mi and the input of the zero setting of the counter duration of failure. The drawing shows a block diagram of the proposed device.

It contains a command counter /, the input of which is connected to the error analysis unit 2, and the output is connected to the unit for the formation and storage of labels, the input of which is connected to the operation control device 4, and the return circuit 5 is connected to the input of the command counter 1. The circuit 6 start-up of the test program, the input of the command counter is connected with the operation control device 4. One of the inputs of the error analysis block 2 is connected to the error detection device 7, the other two inputs are connected by the lockout circuit 8 and the circuit 9 to unblock the call block of the error analysis program are connected to the operation control device 4. An error detection device 7 is associated with a control input of the start block 10 of the failure duration counter, to the frequency input of which a circuit 11 is connected.

feeding the main pulses, and the blocking input - blocking circuit 8 with the device 4 control operations. The output of the block 10 of the start of the counter duration of failure is connected to the counting input of the counter 12 of the spine duration

a fault whose overflow output is connected

with block 13 to generate a signal failure DVR. The information outputs of the fault duration counter are connected to the information inputs of the read valves 14, the control inputs of which are connected to the operation control device 4 by the reading circuit of the fault duration counter 12.

The device works as follows. In the process of executing programs 3, the formation and memorization of labels with the participation of the command counter / and the operation control device 4 produces the formation and memorization of labels, which are returned to when an error is detected in a limited portion of the programs between the labels. If during the operation of the digital computer, the device 7 detects an error, then an error signal is generated at its output, which is output from the device 7 to the control input of the unit 10 and to the input of the error analysis unit 2. After that, the error detection device removes the error signal from its output. Block 10, having received the error signal, remembers it and opens the main pulses of the main impulses access to the main pulses of a known frequency from the main-pulse generator of digital computers (not shown) to the counter 12 of the fault duration, which starts counting the time since the error was detected.

The error analysis block, having received the error signal, interrupts the program and switches the number of the first command of the error analysis program to the command counter 1. Device 4 at the beginning of the error analysis program uses the signal on the test start circuit 6 to switch to the command counter the number of the first command of the test program, the purpose of which is to delay the start of the execution of the error analysis program itself and repeat the program section in the presence of an error. If during the execution of the test program by the device 7, an error is again detected, the error signal is again generated, the test program is interrupted and the test program is run again on the same lines.

During the operation of the test program, the counting time of the counter 12 is counted. If the test program does not complete successfully (the test program runs with errors), the signal from the overrun output of the counter of the duration of the error goes to the signal generation unit 13 failure of the digital computer and causes it to fire. If the execution of the test program is successful, i.e., no error is detected, then the error analysis program generates a signal through the interlock circuit 8 through the operation control device 4. This signal is fed to the error analysis block

and blocks the ability to call an error analysis program, enters the start block 10 of the duration of the failure counter and blocks the access of the main pulses to the counter 12 of the duration of the failure.

Then, device 4 generates a signal to readout circuit 15 for the duration of the fault counter. This signal is applied to the read valves, where the readings of the counter 12 are read, and to the input of the zero setting of the counter 12 for the duration of the fault, as a result of which it is reset to zero. For this reason, the error analysis program proceeds to the analysis of errors and the organization of repetition of the program section, which was initially detected by an error. Immediately before the repetition of the section begins, the error analysis program through the device 4 generates a signal

In circuit 9, unblocking the call to the error analysis program and unlocking it from the error analysis block. The error analysis program, device 4, also generates a signal by which the command stored in block 3 of the return circuit 5 is sent to the command counter and the repetition of the program section where the error was originally detected begins.

Credmet invention

A device for controlling a digital computer, comprising an error detection device connected to the unit

error analysis, the output of which is connected to the input of the command counter, the device for controlling operations, the output of which is connected to the inputs of the block for forming and storing marks and with the input of the error analysis block,

DVM failure signal generation unit, characterized in that, in order to increase the reliability of separating random faults from faults, increase the operational reliability of the DVR and generate data on the duration of faults, it additionally contains a fault duration counter, a start unit and read gates, a counter input of the fault duration connected to the output of the start block, the input of which is connected to the output of the device

error detection, the second input of the start-up unit is connected to the main pulse bus, the third input of the start-up unit is connected to the output of the operation control device, the overflow output of the fault duration counter is connected to the input of the fault output unit CVA1, the information output of the failure duration counter is connected to the readout gate inputs, the second inputs of which are connected to the outputs of the control unit

operations and the installation of the zero-setting counter of the duration of the failure.