SU1660204A1 - Sync pulse separator - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to expand the functionality by extracting the horizontal sync pulses from the sync mixture. The synchronization mixture input to the device, using the first inverter 1 and the second inverter 2, controls the tact advance of the logical units in the shift register 3. The outputs of the shift register 3 are selected in such a way that after the occurrence of a frame sync pulse (XI) in the synchronization mixture, a delayed XI is formed at the output of the first D-flip-flop 4. After the line sync pulse (DFI) appears in the synchronization mixture, the logical unit at the outputs of shift register 3, passing through the OR 6 element, controls the state of the second D-flip-flop 5, at the output of which the delayed DFI is formed. 1 il.

Description

WITH

WITH

8 o / u 2

o o o u o o

N

The invention relates to television technology.

The purpose of the invention is to expand the functionality of the device by extracting the horizontal sync pulses from the sync mixture.

The drawing shows a structural electrical circuit of the proposed device.

The device contains the first 1 and second 2 inverters, the reverse shift register 3, the first 4 and second 5 D-flip-flops and the element OR 6.

The device works as follows.

A synchronizing mix with frame inserts and equalizing 1 / pulses of negative polarity is fed to the input of the first inverter 1, which is a buffer element and serves to generate a signal with the required steep front. From the output of inverter 1, the synchronizing mixture of positive polarity is fed to the information input of register 3 and, as a signal controlling the direction of the shift (for example, summing), to the first control input of register 3, to the right. At the same time, the clock pulses arriving at the clock input of the reverse shift register advance the input signal by register bits 3. If the EOSODN signal from inverter 2 stops, a push signal is generated at the second control input (subtraction (signal from register 3 is left shift When a device receives a horizontal sync pulses with a duration of g PTK, the contents of register 3 increase from n to n, where n is the register bit number; Tk is the period of the clock signals. With the horizontal sync pulse terminated When the signal from inverter 2 is dropped, the single state of the ri-th bit of register 3 is entered into D-flip-flop 5 and a line sync selection signal is generated at its output. Since the signal in register 3 is shifted in the opposite direction during pause, the first bit register 3 will pass to the zero state through n clock pulses and the inverse signal from its output will return the D-flip-flop 5 to the initial state.

When signals that are shorter or longer in terms of horizontal sync pulses (actually interfering with them) are affected at the device input, the pulses in D-flip-flop 5 are not entered, i.e. if the input signal is less, then at the occurrence of a period at the output of the inverter 2, the n-th bit is still in zero

condition; if the signal is greater than the horizontal sync pulse, then the c (n + 1) -th bit of the D-flip-flop 5 through the element OR 6 is locked and the drops at the output of the inverter 2 to it

do not affect. When a frame sync pulse arrives at the input, the contents of register 3 increase and reach the value Xk, i.e. bit HK, and then bit N - the last bit of the register.

Optimal is the choice of N from the ratio of 1.2 TkI

Sheni

Tk

where tki - duration

single personnel impulse between the sidebars. Size X is chosen according to the formula

X

0.5 Tk

At the end of a single human impulse, i.e. during a pause equal to the duration of the tie-in, subtraction occurs

signal. However, before the X-bit of register 3 transitions to the zero state by the front of the next single pulse at the clock input of the D-flip-flop 4, the single state of the X-bit is fed to the input of the D-flip-flop 4 and

its output is formed by a frame sync signal.

After the end of the single frame pulses, the pause increases and by the arrival of the horizontal sync pulse, the discharge Xk appears in the zero state and the front of the horizontal sync pulse D-flip-flop 4 returns to its original state.

Thus, at the output of D-flip-flop 4, a frame sync pulse is generated,

the fronts of which are rigidly associated with the fronts of the signal.

If the input of the device receives synchronization signals without frame impulses and equalizing pulses, the frame

the sync pulse, advancing in register 3, reaches the bit N and translates the D-flip-flop 4 into a single state. At the end of the personnel clock, i.e. during a pause, the signal is subtracted and with the transition of the first

the discharge into the zero state the D-flip-flop 4 goes to the initial state.

Thus, at the output of D-flip-flop 4, a frame sync pulse is generated, which is delayed for the time HxT and equal in duration to the input frame.

Claims (1)

The invention includes a sync pulse extraction device containing a first inverter, the input of which is an input of the device, and an output connected to the input of the second inverter and to the clock input of the first D-flip-flop, the reset input of which is connected to the output of the OR element, characterized in that the purpose of extending the functionality by extracting from the sync mixture of horizontal sync pulses, a shift register is entered in it, the data input and the first control input of which are connected to the output of the first inverter, the second control The input of the shift register is connected to the output of the second inverter and the clock input of the second D-trigger, and the clock input of the shift register is the clock input of the device, the first output of the reverse shift register is connected to the reset input of the first D-trigger and to the first input the item or wto The output of the reverse shift register is connected to the data input of the second D-trigger, the third output of the reverse shift register is connected to the data input of the first D-trigger, and the fourth and fifth outputs of the reverse shift register are connected respectively to the second input of the OR element and the setup input the first D-flip-flop, while the output of the first b-flip-flop is the output of human sync pulses, and the output of the second D-flip-flop is the output of horizontal sync pulses of the device.