SU1762402A1 - Digital pulse-length modulator - Google Patents

Abstract

The invention relates to a pulse technique and is intended for use in communication systems and automatic control systems. The device contains a generator of 1 clock pulses, a binary counter 2, an adder 3, a phase comparator 4. two registers 5, 6, a logic matrix 7, a signal source 8. 1 Il.

Description

-five

fe

Digital pulse-width modulator refers to a pulse technique and is intended for use in communication systems and automatic control systems.

The purpose of the invention is to reduce the conversion error when the digital pulse-width modulator operates at high clock frequencies of the digital pulse-width modulator,

The drawing shows a block diagram of a digital pulse width modulator.

The digital pulse-width modulator contains a clock pulse-pulse generator 1. binary counter 2, adder 3, phase comparator 4, first register 5, second register 6, logic matrix 7, signal source 8, and the output of generator 1 is connected to a counting input binary counter 2. The N bit outputs of which are connected to the first group of N inputs of the adder 3, the outputs of the higher bits of the binary counter 2 and the adder 3 are connected to the inputs of the phase comparator 4. the output of which is connected to the output bus, the outputs of the logic matrix 7 are connected respectively, to the input of the signal source 8 and the control inputs of the registers 5, b, N-1, the bit output of the signal source 8 is connected to the N-1 bit input of the first register 5, the M-1 bit outputs of which are connected to the N-1 bit The second inputs of the second register are 6. N-1 bit outputs are connected to the second group of N-3 inputs of the adder 3, and inputs of the local matrix 7 are connected to the outputs of the binary counter 2.

The device works as follows.

The pulses from the output of the generator 1 are fed to the counting input of the binary counter 2, the outputs of which form N sequences of square pulses, each of which goes to the corresponding bit N of the discharge adder 3, to the second half of which (except for the higher bit) the control is applied binary code from the second register b. In order for the digital pulse-width modulator to work properly, the higher-order input of the second half of the adder 3 must be supplied with a code corresponding to a logical zero. The sequence of the smallest frequency produced by the high-order bit of the binary counter 2. goes to the first input of the phase comparator 4, the second input of which receives the sequence from the high-pass output of the adder 3. The phase shift between the sequences depends on the control binary code on the second half of the adder's inputs 3 (except higher order) than

it is greater, the sequence from the output of the adder 3 is more ahead of the sequence from the output of counter 2 and vice versa. Thus, by changing the code on the second half of the inputs of the adder 3 (except for the higher 0 bit), at the output of the phase comparator 4 it is possible to obtain a pulse-width sequence. In this case, a change in the duration of positive pulses at the output of comparator 4 occurs at a constant period and phase. The frequency of the clock generator 1 should be 2 times higher than the required frequency of the width-modulated pulses, n N-1.

Control code on the second half

The 0 inputs of the adder 3 are determined by the code stored in register 6, the output of which is connected to the second half of the adder 3. The code in register b is replaced every time that voltage levels (corresponding to logical unit, wherein the logic matrix 7 produces gating pulses applied to the control inputs of register 6, and a code is written to register 6,

p stored in register 5. whose outputs are connected to the inputs of register 6. The code recorded in register 5. originates from signal source 8. Moreover, the appearance at the control input of register 5 of the recording pulse 5 that is output from the output of the logic matrix 6. There is a later occurrence of the data request signal to the source 8, originating from the logical matrix 7. The recording pulse delay time

0 of the data request signal from the source 8 is equal to T Tdr + rp, greater than the aperture delay gap time and the aperture bounce rate.

Thus, writing code to register 5

5 occurs after the establishment of stable logic levels on the output bus of the signal source 8 and takes into account the delay of the aperture in the source of signal 8 and taking into account the time of bouncing of the aperture on the output bus of the signal source. At the same time, the control code stored in register 6 does not change, and, consequently, the sequence produced by the adder 3 does not change, as well as the sequence at the output of the device. The entry in register 6 of the new control code occurs only after the next width-modulated pulse has been generated, since this happens not earlier.

the moment when the counter 2 readings are close to the maximum (maximum).

The signal source 8 of a digital pulse width modulator can be a microprocessor system, then the aperture shift in the signal source can be understood as the time spent by the microprocessor system from the moment the microprocessor system starts to process some variable source data until it appears on the output buses signal source code corresponding to the specified source data.

Then the aperture shift can be quite accurately defined as

1 to

fan - 2 d "t I

where fT is the clock frequency of the microprocessor system;

Ci is the number of ticks needed to execute the i-th command;

K is the total number of commands carried out by the microprocessor system required for processing the initial data and issuing a code to the output buses.

If Gap were sufficiently small compared to the period of width-modulated pulses or gap 0, which means that the code on the output buses of the microprocessor system is constant, then the code change on the second inputs of the adder 3 at the time points corresponding to the end of formation a pulse-width modulated pulse would not lead to an error in the operation of the prototype.

However, with an increase in the clock frequency of the clock pulse generator 1, which is necessary in the case of working with the output code of the signal source 8, which has a large width, as well as in the case of an increase in the required frequency of the width-modulated pulses, such a situation can occur, in which the gap can reach unacceptable values.

For example, with a microprocessor-based clock frequency of fT 4 MHz, the maximum possible number of commands needed to process data and issue a code to the output buses, K 30, the average number of clock cycles needed to execute one command. With 9 when the output spacing of the pulse-modulated pulses is 100 microseconds, we have the maximum possible aperture shift

Gap - g K C 67.5 μs, Tt

which is more than half the period of the output pulse-width modulated pulses and is unacceptable because it leads to an error in the prototype, so the microprocessor system may not have time to issue the corresponding code by the time 5 when the digital pulse width modulator starts the formation of the next pulse-width modulated pulse.

Thus, the aperture shift in the considered example is in the limit of 67.5 µs. accepting some intermediate values, since in the general case the microprocessor-based data processing program has 15 traces that can be used to match different gaps in the range from 0 to 67.5 µs and which can be used to compare variable source data. Therefore, the time-averaged error of prototype 0 has the character of a constant error.

When operating in the specified conditions, the proposed digital pulse-width modulator eliminates the possibility of error when the aperture is delayed in the signal source 5-s. at the same time, the gap can be close to the period of the width-modulated pulses.

The 8 working conditions given in this example are possible by the following organization of a digital

pulse width modulator. At a time close to the beginning of the formation of the current width-modulated pulse, the duration of which is determined by the code. 5 stored in register 6, the output of the logic matrix 7 generates a microprocessor interrupt request signal, which begins processing new current data. Since it is known in advance that the aperture shift in the microprocessor system cannot exceed the value of gap after this time of the logic matrix 7, a strobe signal is output to the register 5. In which a new code is written, received - 5 from the output buses of the microprocessor system, and a moment of time close to the end of the current period of the formation of a width-modulated pulse, the logical matrix 7 generates a strobe signal for writing to register 6. into which a new code is written from the output of register 5. Thus, by the time the forts The new pulse width modulated pulse on the second inputs of the adder 3 is equipped with a new code stored in register 6.

Work in the microprocessor system interrupt mode implies the interruption by the microprocessor system of a certain program, for which, in the example given, a time of at least T - gap can be allotted for each period T of forming a pulse-width modulated pulse, i.e. idle times in the processor are eliminated, which is advisable.

Changes can be made to the operation of the proposed pulse-width modulator by various external devices. For example, the signals at the inputs of the parallel load and the control inputs of counter 2 can affect the conversion factor of binary counter 2. Or, for example, signals may be present on the bus connected to the control inputs of the logic matrix 7 indicating an abnormal operation of the signal source 8. For example, the absence of a signal confirming an interruption means an abnormal operation of the logic Coy matrix 1 by outputting signals initializing the external device to eliminate possible errors. The bus connected to the outputs of binary counter 2 can be useful for synchronizing the operation of a signal source, for example, a parallel-type amplitude-digital converter containing gating comparators and encoding logic, while register 5 should be organized taking into account the bounce of the aperture on the output amplitude digital converter, the source of the signal.

The logical functions generated by the logical matrix 7, whose input is connected to the output of binary counter 2, depend on the code at the output of binary counter 2, i.e. from the current time since the beginning of the formation of the next pulse-width modulated pulse. Logical functions generated by the logical matrix 7. must ensure the appearance of signals for requesting data from write gates to registers 5 and 6 at times chosen with regard to the time characteristics of the signal source 8 and corresponding to a specific code on the outputs of binary counter 2. Logical functions generated by the logical matrix 7, if necessary, such a mode of operation of the digital pulse-width modulator, when some of the inputs of the logic matrix 7 receives signals from external devices, to zhny provide normal operation of the digital pulse width modulator and output signals to external devices, if provided.

Logic matrix 7 can be made on the basis of digital integrated circuits of a programmable logic array (PLA), read-only memory (ROM), ROM memory drives, random access memory.

(RAM), combinational logic on integrated circuits of small and medium degree of integration.

The proposed digital pulse width modulator makes it possible to reduce

conversion error when operating at high clock frequencies of a digital pulse-width modulator clock pulse generator. This is achieved by organizing the control of a digital latitude-pulse modulator, in which the temporal characteristics of the signal are taken into account. In addition, a digital pulse width modulator can be provided with the flexibility to make changes in operation during operation and adjustment of the communication system (automatic control system) in which it operates.

Claims (1)

Invention Formula A digital pulse-width modulator containing a signal source, a clock pulse generator, the output of which is connected to a binary counter counting input, N bit outputs that are connected to the first group of N totalizer inputs, the high bits of a binary counter and totalizer are connected to the phase comparator inputs The output of which is connected to the output bus of the device, characterized in that, in order to reduce the conversion error when operating at high clock frequencies, two registers are entered into it and the matrix, the outputs of which are connected respectively to the input of the signal source and the control inputs of the first and second registers, (M-1) -discharge output of the signal source is connected to the (Y-1) -discharge input of the first register (N-IJ-bit one way out 0 which is connected to the (M-1) -digit input of the second register, (M-1) -the discharge output of which is connected to the second group of N-1 inputs of the adder, and the inputs of the logic matrix are connected to the outputs of the binary 5 counters.