SU1474847A1 - Recirculating code-to-time-interval converter - Google Patents

Abstract

The invention relates to computing and can be used to accurately convert a code to the duration of the nanosecond electric signals in experimental physics, radar and industrial electronics. The purpose of the invention is to simplify the converter while maintaining high accuracy. According to the trigger signal, the pulse shaper produces a pulse of exemplary duration, which is introduced into the circulation circuit (time recirculator) formed by AND, OR, selector-multiplexer, discrete delay elements. At the same time, the counting unit calculates the number of recirculations, at the equality of which the input code generates a pulse allowing the output of the signal converter of the corresponding duration. 2 hp f-ly, 2 ill.

Description

one

The invention relates to computing and can be used to accurately convert a code to the duration of the nanosecond electric signals in experimental physics, radar and industrial electronics.

The purpose of the invention is to simplify the converter while maintaining high accuracy.

Figure 1 shows the flowchart of a recirculated code converter in a time interval; Fig. 2 is the same with another possible embodiment of the counting unit.

The Converter (figure 1) contains the element And 1, element 2 delay, se-, lecturer-multiplexer 3, discrete element 4 delay, the counting unit 5,

bus 6 installation, bus 7 start, the element OR 8, the driver 9 pulses, the element 10, the trigger 11, the output bus 12 and the bus .13 input code.

The counting unit 5 can be executed on the pulse counter 14, the code comparison unit 15 and the register 16 (FIG. 1), or on the pulse counter 17, the NOT unit 18 and the reversing counter 19 (FIG. 2).

The Converter operates as follows.

Prior to the start of the conversion by the installation signal, the corresponding elements of the counting unit 5 (counter 14 and register 16 or counter 17 and reversing counter 19) are set to the zero state. With this trigger

Јъ

00ъ 00 Ј

sj

11, by the inverse output, is set to the state of Logic one, and by the direct output, to the state of Logical zero. Thereby, the element 10 is locked and the element 1 is unlocked. Then, on tires 13, the value of the converted code entering the counting unit 5 is set, depending on the performance of which the code value is written either to memory register 16 (Fig. 1) or reversible counter 19 through the block 18 elements NOT (figure 2), By. signal Starting on bus 7, the former 9 generates a rectangular pulse of exemplary duration dt. The value of & t is chosen based on the required accuracy of the conversion and determines the resolution of the conversion. An impulse of exemplary 4t duration is introduced into the circulation circuit (hereinafter in the time recirculator) formed by AND 1, OR 8, selector-multiplexer 3, discrete delay element 4, after which the recirculation process begins. Moreover, during the first recirculation at the output of the element OR 8, a pulse of duration t Xi ut + t 3Ji 2utt is produced where t ez is the delay time of the delay element 2, moreover, it is necessary that At. At the same time, the delay element 2 should have high stability and introduce minimal distortion when the pulses are delayed. During the second recirculation, the output of the element OR 8 produces an impulse of duration t t X (+ t zl zl tl.

Thus, with each recirculation, the initial impulse of exemplary duration dt is consistently expanded by the same value of t ez - Јt. At the same time, the counter 14 (17) of the pulses of the counting unit 5 dehydrates is counting the number of recirculation, while the selector-multiplexer 3 as the counter 14 (17) of the pulses of the counting unit 5 is filled, sequentially switches the delays of the discrete 4.

The discrete delay element 4 is made with n taps, where n 2 - 1j m logt (N Mciw + 1) and is the number of counter bits 14 (17) pulses N max the maximum value of the converted code, and the discreteness of the delay between taps should be t 2it. Total dis latency

n

0

five

specific element 4 delay, i.e. from the first tap to the n-th, equals T ri tj., it should be taken into account that T N MaKC -st.

The switching logic of the taps of the multi-tap discrete delay element 4 is as follows. For example, after the first recirculation, a counter equal to one is fixed in the pulse counter 14 (17), which by means of the selector-multiplexer 3 connects the first tap of the multi-tap discrete delay element 4 (having delay tp with the first output of the first And 1 circuit). a pulse with a duration t Xl 2dt is delayed in the delayed discrete element 4 delays by time t,. After the second recirculation, a pulse of duration t xi t x + t ez, 3dt is delayed in the delayed discrete element 4 delays already at time 2ta.

Thus, as the number of recirculation increases and, accordingly, the contents of the pulse counter 14 (17), the selector-multiplexer 3 switches the taps of the discrete delay element 4, changes its delay time (recirculation period) from t to nt, . The recycling process takes place

It goes until the number of recirculation recorded in the counting block 5 becomes equal to the value of the code to be converted on buses 13, for example / (where A and N is the NMMKC; NMUH is the name of the code to be converted).

In the first embodiment of the counting unit 5 (Fig. 1), the moment of equality of the number recorded in the register 6 with the number recorded in the counter 14 pulses is fixed by the code comparison unit 15, the output signal of which by means of the trigger 11 generates an enable signal to the second element AND 10. At the same time, a pulse signal with a duration tv p at is fed from the output of the selector-multiplexer 3 to the output bus 12. At the same time, the inverse output of the trigger 11 generates a signal, the locking element I 1.

The conversion time at .this is determined by

, -,

where t is the period corresponding to recirculation.

Since t 4l t u g 2t; t

 3t

tu nt

then t

n (n + 1)

 2

rrp -2V

Due to the fact that n

Cc "t a (NwaKC- 1)

- one

T)

1 np -IN MCXKCоJ

The time range of the output pulses of the converter, depending on the value of the code being converted, is (t mind „n - t x” li) where txMUH / it;

t to: moks N 4 t.

I

In the second embodiment of the counting unit 5 (FIG. 2), the converter works similarly to that considered, with the only difference that the value of the converted code after inversion in block 18 of the elements is NOT recorded in the reversible counter 19. With this calculation, the number of recirculation is on the input of the summation of the reversible counter 19 until the moment when an overflow pulse appears at its output, which flips trigger 11 and carries out the output from the temporary recirculator to the output bus 12 of the pulse whose duration is Substituting the result is a code conversion to the time domain. Block 18 elements can NOT be excluded. Then the converted code must be directly fed to the pre-recording inputs of the reversible counter 19. In this case, the counting number of the recirculation will be performed on the subtraction input of the reversible counter until the zero signal appears at its output. This signal by means of a trigger 11 recirculator of the result of the conversion code in the duration.

Claims (3)

Invention Formula 1, the recirculation converter of the code in the time interval containing the first AND element, the output of which is connected to the first input of the OR element, the delay element, the trigger, the first output of which is connected to the first input of the second And element, and the counting block whose information inputs Input code buses, characterized in that ten 15 ; 20 . 25 30 -ts 40 45 5Q 55 that, in order to simplify the converter while maintaining high accuracy, it introduced a discrete delay element, a selector-multiplexer and a pulse shaper, whose input is a trigger bus, and the output is connected to the second input of the OR element, the third input of which is connected to the output through the delay element The first element And, the first input of which is combined with the second input of the second element And and connected to the output of the selector-multiplexer, and the second input is connected to the second output of the trigger, the R-input of which is combined with the input set The counting unit is the installation bus, and the S input is connected to the information output of the counting unit, the control outputs of which are respectively connected to the control inputs of the selector-multiplexer, the information inputs of which are connected to the corresponding outputs of the discrete delay element, the input of which is combined with the counting input counting unit and is connected to the output of the OR element, and the output of the second element AND is the output bus. 2. The converter according to claim 1, T is characterized in that the counting unit is executed on a register, a code comparison unit and a pulse counter, the counting input of which is the counting input of the counting unit, the installation input is combined with the register installation input and is the installation input the counting unit, and the outputs of the pulse counter, respectively, are connected to the first inputs of the code comparison unit and are the corresponding control outputs of the counting unit, the information output of which is the output of the code comparison unit, the second inputs of which respectively connected to the outputs of the register, the information inputs of which are the corresponding information inputs of the counting unit. 3. The converter according to claim 1, T is characterized by the fact that the counting unit is made on the block of NOT elements, the reversible pulse counter and the pulse counter, the counting input of which is combined with the summing input of the reverse pulse counter and is the counting input of the counting block, the input setting pulse counter combined with input us714748478 The settings of the reversible counter are impulsed to the corresponding inputs of the power unit and it is the input of the installation of counters NOT, the outputs of which are connected unit, and the outputs of the pulse counter to the corresponding information inputs are the corresponding outputs of the reverse pulse counter, The control units of the counting unit whose in-output is the informational inputs of which is the output of the counting unit. Launch but Fie.2