SU1751845A1 - Pulse-width modulator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital information conversion systems, in particular, for constructing digital-analog converters. The purpose of the invention is to expand the field of application and increase the reliability of the device — achieved by introducing a pulse-modulator into the pulse-width modulator, which contains a pulse generator 1, a trigger 4 and a reversible counter 2, a short pulse generator 5 and using a counting trigger as a trigger 4. The introduced differences allow the formation of a pulse-width-modulated signal in the absence of an external control signal, as well as reduce hardware costs for the implementation of the device and, consequently, increase its reliability.

Description

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The invention relates to a pulse technique and can be used in digital information conversion systems, in particular, for building digital-analog converters.

A device of similar purpose is known comprising a pulse generator, an adder, a counter and a phase generator.

A disadvantage of this device is its complexity and, as a consequence, low reliability due to the presence of a multi-digit adder of two numbers and a phase comparator.

The closest technical solution to the present invention is a pulse-width modulator containing a pulse generator, a reversible counter, two RS-flip-flops, a two-input element AND, a three-input element AND-NOT, a three-input element AND-NOT with one inverse input, an input strobe pulses.

The main disadvantages of this device are: the complexity of the known device, and as a result, low reliability, due to the presence of two RS-flip-flops, two AND-NOT elements and an AND element; as well as a narrow field of application, due to the necessity of gating the operation of the device with a special input signal.

The purpose of the invention is to expand the scope and increase the reliability of the device.

The goal is achieved in that a pulse width modulator containing a pulse generator, a trigger and a reversible counter, whose information inputs are the binary bits of the device, is entered into a short pulse shaper, and the trigger output of the counting pulse is connected to the input of the counting direction a reversible counter connected by a clock input to the output of the pulse generator, and a presetting enable input to the clock input of the trigger and through a short pulse shaper from the output reversible counter overflow home.

The drawing shows a functional diagram of a pulse width modulator.

The pulse width modulator contains a pulse generator 1, the output of which is connected to the clock input of the reversible counter 2, the information inputs of which are the inputs of 3 binary bits of the device, the counting trigger 4, the clock input of which is connected to the resolution enable input of the reversible counter 2 and the output

a short pulse generator 5, the input of which is connected to the transfer output of the reversible counter 2, the counting input of which is connected to the output of the counting trigger 5, which is the output 6 of the device.

Pulse width modulator operates as follows.

Converted into a pulse-width modulated signal, a binary code corresponding to a decimal number A, is fed to the inputs of 3 binary bits of the device and does not change during the considered period of operation.

5 1 continuously generates pulses with a repetition period To, the counting of which is performed by the reversible counter 2. In the direct counting mode, a code combination at the outputs of the binary bits of the reversing

0 counter 2 (not shown in the drawing) becomes maximum, containing only logical units, the voltage level at the transfer output of the reversible counter 2 changes from high to low. With the arrival of the front of the next pulse from the output of the generator 1 to the clock input of the reversible counter 2, it passes to the state containing only logical zeros. In this state, the transfer output state of the reversible counter 2 changes from low to high. This positive voltage drop is applied to the input of the driver 5, which forms at its output a short pulse of duration

5 to To, the front of which coincides with the front of the pulse at the output of the reversible counter 2, This pulse causes the switching of the counting trigger 4 at its clock input and the presetting of the reversible counter at its permission enable of the preliminary installation. In this case, a code combination is set at the outputs of the binary bits of the reversible counter 2, equal to the binary code at the inputs 3

5 of the device, corresponding to the decimal number A, and the counting trigger 4 goes from state 1 to state O, the low voltage level at input 6 of the device and input of the direction of the reversible counter 2 transfers it to the countdown mode. After time (А + 1) After setting the device output B to the state O, the code combination at the binary bits of the reversible counter 2 of 5 changes from a state containing one logical zero to a state containing one logical one. In this case, a positive voltage drop appears at the output of the reversible counter 2, which leads to the appearance at the output of the shaper 5 of a short pulse of duration to. This pulse causes the switching of the counting trigger 4 from the state O to the state 1 and the setting of the binary bits of the reversible counter 2 of the code combination equal to the binary code at the inputs 3 of the device corresponding to the decimal number A. As a result of the switching of the counting trigger 4 The output 6 of the device is set to state 1, which switches the reversible counter 2 to direct counting mode upon its input to the counting direction. After a time (2 - A) So after the last switching of the counting trigger 4, where N is the number of bits of the reversible counter 2, the code combination at the outputs of the binary bits of the reversing counter 2 changes from a state containing one logical unit to a state containing some logical zeros. In this case, a positive voltage drop appears at the output of the overflow of the up-down counter 2. The process then repeats. As a result, a pulse-modulated signal with a repetition period of (+ 1) To is formed at the output 6 of the device. The duration of the pause between pulses is (A + 1). This corresponds to the binary code at the inputs 3 of the device.

Claims (1)

The use of a pulse width modulator makes it possible to expand the field of application of the device by ensuring the formation of a pulse width modulated signal in the absence of an external control signal. The introduction of a short pulse to the pulse-width modulator of the former 5 and the use of the counting trigger 4 reduce the hardware implementation costs and improve the reliability of the device. A pulse width modulator comprising a pulse generator, a trigger and a reversible counter, the information inputs of which are the binary bits of the device, characterized in that, in order to expand the field of application and increase the reliability of the device, a short pulse shaper is inserted into it, and the output of the trigger, made by counting, is connected to the input of the counting direction of the reversible pulse counter connected by a clock input to the output of the pulse generator, and the input of the resolution is preceded by noy installation - a clock input of the flip-flop and through a shaper short pulses - yield overflow down counter.