GB1462617A - Analogue to digital converters - Google Patents

Abstract

1462617 Analogue to digital converter SOLARTRON ELECTRONIC GROUP Ltd 1 May 1974 [5 May 1973 (2)] 21513/73 and 21514/73 Heading H3H In a dual ramp analogue to digital converter for A.C. or D.C. with an unwanted periodic noise signal, the duration of the ramp for which the unknown voltage is applied is made equal to an integral number of cycles of the A.C. or periodic noise. The integrator operates in two modes. The first mode has time constant T 1 and integrates both A.C. and D.C. while the second mode has time constant T 2 and integrates A.C. only. The system is initially in the first mode, and integrates the unknown voltage for fixed time T 2 in the first mode and then switches to the second mode until the end of the next A.C. cycle. These together constitute the up ramp. The down ramp is generated by a reference voltage and the digital signal is derived from its duration. As shown, the unknown voltage is applied at 10, S A being closed to short out Cin for a D.C. voltage. The A.C. component passes C 2 to threshold circuit 32 which has an output whenever the voltage at 31 is greater than Œ#. The threshold circuit output is supplied to anti-jitter circuit 36 which is also supplied with clock pulses from 40. The circuit 36 cleans up the edges of square wave pulses which result from the threshold circuit. The output of the anti-jitter circuit sets bistables 52 and 54, permitting clock pulses to pass gate 74 to counter 70 and enabling gate 58 so that square pulses from the threshold circuit operate switch S 1 and function as a synchronous rectifier supplying A.C. to the integrator 16. With a D.C. input, switch 66 is against contact 64 and switch S1 is permanently closed. When counter 70 is full (6000), bi-stable 80 is set and closes S2 to change the integrator time constant to T 2 . At the next pulse from the antijitter circuit 36, bi-stables 80 and 54 are reset, bi-stable 88 is set and the set output of this bistable resets bi-stables 52 which renders S1 inoperative via gate 58 and resets counter 70. S3 is also closed by bi-stable 88 applying reference voltage 24 to the integrator which now has time constant T 1 . Clock pulses pass via gate 74 to the counter until the input of comparator 28 reaches zero when bi-stable 88 is reset, gate 74 closed and the counter reading transferred to display 94. In an alternative embodiment a rectifier may be incorporated in series with the integrator capacitor C1.