SU414743A1 - COUNTER WITH ACCOUNT COEFFICIENT 2 "—2 '^' ' - Google Patents

Description

one

The invention relates to computing technology. The device can find the pr-name B digital computers.

Known counters. With a coefficient of reciprocal 2-2 + 1, containing-bit binary counter. With a blocking circuit at the input, n-bit discharge binary counter with the scheme of linking units and .the entrances of the blocking circuit and the schema of the end-to-end transfer are connected to the source of input signals, the second circuit. the second circuit is blocked, it is connected to the direct output of the co-ownership unit, the inverse of which is connected to the second input end-to-end transfer schemes.

The known counters are rather complicated, and for the selected number of countable tr. Iggers, the conversion factor is a fixed value.

The purpose of the invention is to expand the functionality of the device. It is achieved by the fact that the output of the -discharge binary counter is connected to the input of the nth-digit binary counter via the OR circuit, the second input of which is connected to the output of the through-transfer circuit.

The drawing shows the functional scheme of the proposed counter.

The counter consists of / e-bit binary counter 1 with blocking circuit 2, pk

bit counter 3 and the co-owned unit 4, .inverter 5, end-to-end transfer circuit 6, the output is the output of the counter, circuit ILI-L 7 and the source of input pulses 8.

The impulses from the source input pulses 8 arrive simultaneously at blocking circuit 2, in the initial state, unlocked by the resolving notable from the coincidence circuit of units 4, and the end-to-end transfer circuit 6, in the initial state and locked by the inhibitory potential from inverter 5.

During the first input pulses, the device operates as a binary counter: 1k: the triggers of the d-bit binary counter / are set to zero, and the triggers of the n- / g-bit binary counter 3 are set to one. G1nn this, on the falling edge of the 2-2nd input and the pulse, the signal at the output of the common control circuit, unit 7, changes by the value of connecting to its inputs the typical outputs of the counting trigger / -disk binary counter 3 changes: at the end of the account and the hive.

So the next 2 -2 + 1-out

the input pulse does not pass through the locked

c.hu.mu lock 2, and through the scheme c.

transfer 6 enters the input device and

at the same time through the scheme "OR 7-on the counting input of the first trigger of the n-bit digital binary counter 5, returning all) the iB and the i-th state.

During this momentum The counter output appears with a delay time delay of the input pulse (delay in the pass through transfer circuit b), and returned, when the counter returns to its original state, and as well as the output pulse terminates, resulting in high response speed .

PRIOR TEDAWS

Counter with counting coefficient, containing / g-, bit binary counter

with the input interlocking circuit, a binary binary counter with ovia-aep units and a front-end circuit, the first inputs of the interlock circuit and the front-end circuit are connected to the source of input pulses, the second inlet of the block circuit is connected to the direct output of the coincident units Inverted output which is united with a second input of the end-to-end transfer scheme, characterized in that, for the purpose of extending the functionality of the functionality, the OUTPUT / e-bit binary counter is connected to the input of the m / z-th bit binary .score Chika through the OR circuit, the second input of which is connected with the output of the end-to-end transfer scheme.

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