SU447844A1 - Decimal counter - Google Patents

Description

one

The invention relates to functional units of computing devices.

Known are decimal counts, containing potential triggers with separate inputs, two of which form 5 count cells, AND schemes for each trigger input, output AND circuit, input NOT circuit, Input and Output buses.

The circuit of the invention is to simplify the device and increase its reliability. 10

This is achieved by the fact that it contains five potential triggers with separate inputs, each input of at least one of the triggers with the I.PI circuit, which has two inputs, which are connected to two circuits AND, respectively, the Input bus is connected to one of the the inputs of the circuits AND of the single input of the first trigger and the circuits AND of the third trigger, the output of the circuit is NOT connected to one of the inputs 20 of the circuits AND the zero input of the first trigger and the circuits AND of the second trigger, the zero output of the first trigger of the counting cell is connected to one of the inputs of the 6 unit in Ode to odd triggers, and 25

single output - with the second circuit AND of the single input of the first trigger and the circuit AND of the zero input of the third trigger, while the zero output of the second trigger of the counting cell is connected to one of the inputs of the first circuit And the zero input of the first and second triggers, and the single output with the second circuit And the zero input of the trigger and the And circuit, the single input of the second trigger, the zero output of the first trigger is connected to ntl from the circuit inputs And the subsequent trigger, and the single output to one of the inputs of the circuits And the last trigger, zero output The second trigger of the main scaling circuit is connected to one of the inputs of the second circuit AND the single input of the first trigger and the circuit AND of the single input of the third trigger, and the single output is connected to one of the inputs of the first circuit AND of the single input of the first trigger and zero output of the third trigger, zero output which is connected to one of the inputs of the second circuit AND the zero input of the first trigger and the circuit AND zero input of the second trigger, and the single output is connected to one of the inputs of the circuit AND of the single input aS of the second trigger and the first circuit AND. Nya Ullevi input of the first trigger. The diagram of the fedl is shown (Gheme counter. It includes potential triggers 1-5 with separate inputs, OR schemes: 6 and 7, AND 8-2O schemes, NOT 21 input scheme, Input and Output buses. Schemes OR 6 and 7 can be implemented using one of the AND diodes connected to the input of the circuit OR the potential trigger A. The device works as follows. When the first impulse arrives, a single potential appears at the Input, which changes the state of the trigger 2; then a single potential appears at the output of circuit 21 and, after circuit 8, changes the state of flip-flop 1. At the moment of arrival of the second pulse, a single potential appears at the Input and, having passed through circuit 11, returns trigger 2 to the initial state imie, and also, having passed circuits 12 and 6, changes the trigger state a 3. Then, a single potential appears at the output of the circuit 21, which, having passed through the circuit 9, returns: the trigger 1 to the initial state. From the third impulse, first appears the same potential at the input, which, circuits 1O and 18, changes the state of flip-flops 2 and 5, then a single potential at the output appears 21; And, having passed through circuit 8, changes the state of trigger 1. At the moment of arrival of the pulse, a single potential appears at the Input, which, having passed through circuit 11, returns trigger 2 to its initial state, then a single potential appears on the output of circuit 21 and, having passed circuit 9, returns trigger 1 to the initial state, and also, having passed circuit 14 and 7, returns trigger 3 to its original state. From the fifth pulse, a potential appears at the beginning at the Input, which, after passing through circuit 1O, changes the state of flip-flop 2, then a single potential appears at the output of circuit 21, and, 1FODE lock 8 and 16, changes the state of flip-flops 1 and 4 .; At the moment of arrival of the sixth impulse; Initially, a single potential appears at the Input, which, having passed through circuit 11, returns trigger 2 to its original state, then a single potential appears at the output of circuit 21 and, after passing through circuit i, returns trigger 1 to its original condition. From the seventh pulse, a single potential appears at the Input, which, after passing through circuit 1O, changes the state of flip-flop 2, and also, goes through circuit 13 and changes the status of flip-flop 3. Then the unit turns into a tilt. the output of circuit 21 and, after passing through circuit 8, changes the state of flip-flop 1. At the moment / arrival of the eighth pulse, a single potential appears at the Input, which, after passing through circuits 11 and 19, returns triggers 2 and 5 to the initial state, then a single potential appears at the output of the circuit 21 and, 1-way circuit 9, returns the trigger 1 to the initial state. From the ninth pulse, a single input appears at the beginning, which, having passed through circuit 1O, changes the state of flip-flop 2, then a single potential appears at the output of circuit 21 and, having passed through circuit 8, changes the state of flip-flop 1, and Also, the circuits 15 and 7 pass through, trigger 3 returns to i idle state. At the moment of arrival of the tenth Pulse, a single potential appears at the Input, which, after passing through circuits 11 and 20, returns trigger 2 to the initial state and arrives at the Output, then appears to be a single potential at the output of operating 21 and, after passing through 9 and 17, returns triggers 1 and 4 to the initial state, with the entire circuit returning to the initial state. The table shows the sequence of states that the triggers take in each of the two clock cycles when ten counting pulses arrive at the Device Input. 56

Impulses Tactics ipErrepm.

447844

Baseline

7 The subject of the invention is a hex {th counter, containing potential triggers with separate inputs, two of which form a counting circuit, circuit AND for each trigger input, output circuit AND, input circuit NOT bus Input and Output, circuit o r h and so that, in order to simplify and increase reliability, it contains five potential triggers with separate inputs, each input of at least one of the triggers is connected to an IL circuit having two inputs, which are connected to two circuits AND, respectively, one of the inputs c m And the single input of the first trigger and; schemes of the third trigger; the output of the IW circuit is connected to one of the inputs of the And zero input circuits of the first trigger and the And second trigger circuits; the zero output of the first trigger of the counting cell is connected to one of the inputs of one circuit And the odd single input flip-flops, and the unit output - with the second circuit AND the unit input of the first trigger and the circuit AND zero input of the third trigger, while

8 zero output of the second trigger of the counting cell is connected to one of the inputs of the first scheme And the goal input of the first and second triggers, and the transceiver output is connected to the second scheme And the zero input of the primary circuit and the simple input of the first trigger is connected to one from the inputs of the And circuit and the subsequent trigger, and the single output with one of the inputs of the And circuits: the next trigger, the zero output of the second trigger of the main conversion circuit is connected to one of the inputs of the second circuit And the single input of the first trigger and, S and a single input of the third trigger, and a single output connected to one of the inputs of the first circuit AND the single input of the first trigger and the circuit And the zero input of the third trigger, the zero output of which is connected to one of the inputs of the second circuit And the zero input of the first trigger and circuit And zero the input of the second trigger, and the unit output with one of the inputs of the circuit AND the single input of the second trigger and the first circuit And the zero input of the first trigger a.

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