SU966890A1 - Code-to-frequency converter - Google Patents

Description

The invention relates to computing and can be used in devices where code-frequency linear conversion is necessary with the ability to control the initial phase of the output signal.

A known code-to-pulse converter is used, a pulse following frequency, a holding two logical circuits AND, an inverter, a comparison unit, a pulse generator, a controlled frequency divider, a number code register, a numeric register; additional control trigger ,, three input buses, a reset bus, a counter of inverse values, a read block, a sum counter, a second comparison block, an input Bus and n triggers

This converter allows to obtain a linear relationship between the input code and the output frequency of the output pulses, but it is highly complex and cannot control the initial phase of the output signal.

A known converter of the QD chitote contains an adder, n outputs connected to the n first inputs via an n-bit register.

and the transfer output to the output through the forming unit, and with the second inputs to the converter moves, with the gate inputs of the forming unit and the n-bit register being connected to the clock input of the converter t2j.

This converter is characterized by simplicity of the circuit design, but its functionality is limited, since it is impossible to control the initial phase of the output signal on it.

The aim of the invention is to expand the functional possibilities.

The goal is achieved by the fact that a frequency code containing the adder is connected to the converter, the first inputs connected to the input code bus, the second input inputs to the register outputs, and the transfer output of the nth digit to the information input of the output unit, the clock of which connected to a clocked register input and a clocking bus, we will additionally introduce a multiplexer, the first group of inputs of which is connected to the corresponding outputs of the adder, the second group of inputs - to the phase setting bus, the control input - to the control laziness, and n outputs - to the corresponding inputs zgistra.

FIG. 1 shows a block diagram of a converter; 2, timing diagrams for his work; Fig. 3 is a block diagram of the output converter unit.

The converter contains a combinator 1 1 i The first n inputs of the adder 1 are connected to the input code 2 bus of the converter, and the second n inputs of the adder 1 to the outputs of the n-bit register 3, the information inputs of which are connected to the outputs of the multiplexer 4. Multiplexer 4 with its first The n inputs are connected to the bus of the installation of phase 5 of the converter, the second n inputs to the outputs of the adder 1 / and the control input to the control bus 6 of the converter. The transfer output of the n-th bit of the adder 1 is connected to the information input of the output unit 7, the clock input of which is connected to the clock input of the register 3 and to the clock bus 8 of the converter.

The converter works as follows.

The binary number F is applied to bus 2, and the number f is applied to bus 5, and an impulse signal with a frequency, j

On the control bus 6, a low potential is set, which indicates that the multiplexer sends the number P with the input 5 to the input of register 3. Since clocked impulses arrive continuously, the number of H is also set at the outputs of register 3, and the number So С - F.

From the moment when the unit (high potential) is established on the control bus b, multiplexer 4 switches to other inputs from the outputs of the adder 1. A closed ring is formed: multiplexer 4, register 3 and adder 1. As the clock pulses, the state of the outputs of the register 3 for each Clock pulse is increased by F until the value 5y at the outputs of adder 1 exceeds. At this moment, a one is formed at the output of the transfer of the n-th bit of adder 1, and -2 F at the other outputs, and so on. In this case, if the value of F is not a multiple of 2, the initial state in register 3 is restored in 2 pulses, i.e. After 2 pulses, the state of the outputs of register 3 is equal to V Pri in the cycle time Ti and the passage of 2 clock pulses, it is possible to determine the number of pulses generated at the n-th bit transfer output, and hence the average frequency of the generated pulse sequence. The number of pulses is obviously equal to F, t & k as in the F- 2 number. F determines how many times the value 2 -1 was exceeded, which is identical to the appearance of the unit transfer. Time of one cycle

- 2

Gr p

and frequency f

wed

The average period of the pulse sequence from the transfer output of the adder is 1 tr.

-r- not divisible in general terms

tea The actual value of the period over time can take up to two values of t and -Sf, differing from each other in duration on the PO closest in value to -PsrH Tf Cc; p-g Gf,). A certain number of periods Tf and tg per Bpet / and Tz cycle gives the average value of the period not multiple / Co. The distribution over the TC and the position position C and f: is determined, obviously, by the value t on the phase setting bus 5.

The above can be illustrated by the example of a four-bit converter for a specific F 7 value. Based on the ENERGED reasoning in Fig. 2, time diagrams of pulse sequences from the n-th discharge output of adder 1 are plotted for all jp values, where m is the sequence number of the clock pulse after unit installation on bus control b.

As can be seen from diagrams, the number of units coincides with the number F. The number of Russian Federation is equal to 5, and the Tuff is equal to 2.

By a detailed examination of the time diagrams, it can be concluded that the value of the number ..H determines the number of clock cycles involved in the advance, with respect to the case when f 0.

So, for example, if we number each pulse corresponding to the unit on the transfer of n-th bit of adder 1 in such a way that it corresponds to the first one with the minimum value t, yak shown in Fig. 2, then it is seen that between sequences f 0 and f 1 shift to one clock pulse corresponds to number 4, and for: 15 the first, second and third pulses are shifted by two clock cycles, the fourth pulse is shifted by three clock j – j fifth, sixth and seventh pulses by two clock cycles, overall, the overall shift is 15 clocks. Thus, it can be argued that the number f corresponds to the number of shifts in the sequence relative to 0. It is possible, based on the given reasoning, to determine the shifts per cycle per pulse and one cycle. t -fE2 .. CpCAfe- f. The output unit 7 is designed to convert the generated stream of pulses from the transfer output of the adder 1 to the desired waveform. In the simplest case, this may be a scheme (see Fig. 3), operating in the centering mode of the process with its subsequent filtration. In this scheme, trigger 9 operates in the counting mode and, at the same time, at its output we have a sequence anoshogichnyi clippedHotJty sinusoidal signal, passed through a sampling device with a sampling frequency fp. The pulse period from the output of the trigger 9 is equal to T V. To isolate the main harmonic of the signal at the output of the trigger 9, a narrow-band filter 10 is set with a sufficiently large time constant. When Tc changes | the phase shift of the filter 10 causes a change in the phase shift, the value of the phase shift can be determined from the expression. From this expression it can be seen that the discreteness of the change in the phase shift within IP is determined by the transducer size n and For the case when the value of the F number at the input is 5 times, where, the phase change resolution is increased 2 times and the ravitieshift is increased by 180 Phase switching by presetting the IoBki flip-flop 9 at inputs 11 or 12. Phase resolution is determined not only by the resolution the driver, but also the output unit circuit 7. Thus, the frequency η {) is set to the code installed on the inputs 2, and the frequency setting resolution is -, is determined by the size of the converter. At the same time, the phase of the output signal is controlled in the converter, and the average phase of the signal is proportional to the code set at converter inputs 5, while the discreteness of the installation is also determined by the size of the converter. invention code converter is the frequency containing the adder, the first n inputs connected to the input code bus, the second n inputs to the register outputs, and the n-th bit transfer output to the information input of the output block, the clocked input of which is connected to the clock input of the register and a clocking bus, which is characterized by the fact that, in order to expand its functionality, a multiplexer is introduced in it, the first group of inputs of which is connected to the corresponding outputs of the adder, the second group of inputs - to the phase setting bus, control input to the control bus, and n outputs to the corresponding register entries. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 677095, cl. H 03 K 13/02, 1979. 2. USSR copyright certificate lo no. 2820488 / 18-24, cl. H 03 K 13/02.

J.S jnJFLJJL-J LJ lJ7l

f.JTUFLfjlJTlfjLJRJTLJiUIU

j.2-Jn-JnJlOn - J5URj7U fJL

Claims (2)

SUMMARY OF THE INVENTION ✓ 25 Converter code - frequency containing the adder, the first η inputs ^ connected to the input code bus, the second η inputs to the register outputs, and the transfer output of the nth 30 bits - to the information input of the output unit, the clock input of which is connected to the clock input of the register and the clock bus, which is different 35 that, in order to expand the functionality, a multiplexer is introduced into it, the first group of inputs of which is connected to the corresponding outputs of the adder, the second group of 4Q inputs on the inputs to the phase setting bus, the control input to the control bus, and η outputs to the corresponding register inputs . 45 Sources of information taken into account in the examination 1. USSR copyright certificate No. 677095, cl. H 03 K 13/02, 1979. 2. USSR copyright certificate. By application W 2820488 / 18-24, cl. H 03 K 13/02. Lee. /