SU405180A1 - RING COUNTER ON POTENTIAL LOGICAL ELEMENTS <gI —NO ”,“ OR —NE ” - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used, in particular, in the construction of simple and economical time keepers, synchronizers and discrete delay lines.

Known ring counter containing the installation bus and the input bus.

For the purpose of improving the each bit of the proposed ring counter, there are three “AND – NOT (“ OR-NO) ”elements, with the output of the first i-fo element of the ring counter being connected to the input of the second element of its bit and to the inputs of the first and second elements ( / + 1) -th bit, the output of the second element (-th bit is connected to the inputs of the first and third elements of its bit, and the output of the third element of the i-th bit is connected to the input of the second element of its bit and to the input of the third element (i-1) -th bit, the inputs of the first elements of all bits about edineny and connected: to the input bus and the second input element of the first discharge cells and third inputs remaining bits are connected to the mounting rail.

} 1a of FIG. 1 shows a schematic diagram of the proposed ring counter at potential potential elements.

"AND-NOT," OR-NOT; in fig. 2 Figures of voltages at the corresponding points of the circuit, explaining the operation of the device.

An annular counter on potential log elements "AND - NOT," OR - NOT represents / (serially connected bits (/ C - division ratio)

with direct and feedback, has a counting (clock) input 1 and input 2 of the installation.

Each bit of the counter consists of three logic elements (3-5 for the first bit, 6-8 for the second bit, 9-11 for the last) and consists of two triggers with one common element (4 times the first, 7 for second, 10 - for the last bit). The bits are interconnected by two outputs and two inputs. So, exit

elements 3, 6, ..., 9 is used to communicate with the next-bit, the output of elements 5, 8, ..., is related to the previous bit. The signal from the next bit arrives at the elements 5, 8, ..., 11, and the signal of the previous bit arrives at the other two elements of each bit. In addition, the clock pulses are sent to the elements 3, 6, ..., 9, and the initial setup pulse is given to the elements 4, 8, ..., 11.

The operation of the device is explained in the stress control diagrams shown in FIG. 2. For a logical “O, a low potential is accepted, for a logical“ L is high. After the initial installation with no signal at input 1 "O

the initial state of all bits except

first, there will be “O on the common element 7, 10, etc. triberov and“ 1 on the remaining arms of the trigger scheme. For the first, the parochial state is "O on element 5 and" 1 pa of elements 3 and 4. At "1 clock cycle on the input of element 3," O appears, which detects the state of the second bit. In this time interval, the steps of elements 6 and 7 will be “1, and of element 8, the logical“ O. The output signal Sigpal of element 8 is fed to the input of element 5 of the first bit. As a result, the state of the first bit is as follows: "1 elements 4 and 5 and" O on the element 3. With the arrival of the clock "O, the state of the second bit does not change. In this time interval on elements 6 and 7 will be “1, on element 8 -“ O. The state of the first discharge is as follows: on element 4 "O, on elements 3 and 5" 1. Thus, during the time interval equal to the non-period of the repetition of clock pulses, the second discharge of the ring counter changed to the state that was at the initial moment of the first discharge, and the first discharge passed to the state that was patched for the second discharge. . It can be shown logically that for the next period of clock pulses, the state of the second bit will be rewritten to the third, and the second bit will return to the initial state, etc. After a time equal to K periods of the input frequency, the state of all bits of the ring counter corresponds to dividing by / S, if the input signal is received from any element of the ring counter, depending on the desired polarity, duration and origin.

Subject invention

An annular counter on potential logical elements "AND - NOT," OR - NOT, comprising an installation bus and an input bus, characterized in that, for the sake of simplification, each bit of the ring counter contains three elements "AND - NOT (" OR - NOT) , the output of the first j-ro element of the ring counter is connected to the input of the second element of its bit and to the inputs of the first and second elements (ifl) -ro of the bit, the output of the second element of its digit is connected to the inputs of the first and third elements of its bit yes, and the output of the third element of the / th discharge chen to the input of the second element and its discharge to the entry of the third element

(d-1) -th bit, the inputs of the first elements of all bits are combined and connected to the input bus, and the input of the second element of the first bit and the inputs of the third elements of the remaining bits are connected to the installation

tire.

In code 1

6 g

J pop

8klepoda code 4

Eepent 5 out

Take out the add-on. 6

Output zlemeyupa 7

The output of the element. eight

1st cut

t-a bit

S-U. dd