SU1270891A1 - Function counter - Google Patents

Abstract

The invention can be used as a counter of a controlled generator of code sequences and a multimode level distributor. The purpose of the invention is the extension of the functionality and application area of the device. The counter contains N bits, each of which is performed on a 1K trigger, and an AND 4 element. The introduction of the AND 5 element, the OR 7.1-7.N-1 elements, and the control bus 6 at each time except the first provides additional code sequence, in particular self-contained code. 3 il. W

Description

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ABOUT

00 with srigL out. N, BbixN The invention relates to a pulsed and computing technique and can be used as a counter of a controlled generator of code sequences and a multimode level distributor. The aim of the invention is to extend the functionality and scope of the counter by obtaining an additional code sequence (in particular, self-contained code 5), FIG. 1 shows a diagram of an N-type functional counter; in fig. 2. and 3 are tables of different code sequences being formed for different values of the number of bits N. The functional counter contains N bits, each of which is performed on the IK trigger 1.1-1.N, the sync input and the input of the zero setting connected, respectively, to the clock bus 2 and the bus 3 of the zero setting, the first element 4, the first input of which is connected to the direct output 1-K of the second discharge trigger 1.2, the second element 5, the control bus 6 and in each section, except for the first, the element OR 7 .1-7 .N-1 ,, the output of each of which is connected c1-in at a time, the 1-K trigger of its bit and the first and second inputs of the OR elements of all bits except the last are connected to the direct outputs of the 1-K triggers of the previous and subsequent bits, respectively, the first and second inputs of the OR element of the last bit are connected with direct output 1-K of the penultimate trigger and inversion with 1-K trigger of the first discharge, output and second input of the first element And connected with 1 input of 1-K trigger of the first discharge and control bus, first input of the second element And with one with the direct output of 1-K trigger of the second bit, and the second input of the second element I and K inputs 50

1-K triggers of the first and second bits are connected to the direct output of the 1-K trigger of the last bit, the output of the second element I is connected to the K inputs of the 1-K triggers from the third to the last bits.

Functional counter works as follows.

Claims (1)

subsequent switching cycles occur alternately filling in with trigger units from the second to the last bit (in direct order). In the last cycle, all 1-K triggers are set to zero initial states. This completes the first cycle of code combination formation. To create each of the possible modes of generating code combinations via bus 3, all the meter triggers are set to the zero initial state, and zero (O) or a single (1) level of logic potential is applied to bus 6. When a zero potential is applied to the bus 6, the logic element 4 is locked at the input and its zero potential keeps the I-K TpHirep 1.1 in a constant zero logical state. With a continuous arrival to the bus 2 of the clock pulses I-K, the triggers are alternately (in reverse order, starting with the last (N-ro) bit) set to one logical state. In the last cycle of the arrival of the clock pulses to bus 2, all the counter triggers are set to zero initial states. This completes the first cycle of forming linearly increasing code sequences. Subsequent cycles of forming these codes are similar to the first cycle described. The repetition periods of these code combinations are determined by the expression T Nrt, where t is the duration of one recalculate cycle. Logic element 4 is introduced into the overall process of the counter operation. When applying to the pin 6, there is one logical level of potential. At the same time, the trigger triggers alternately in reverse order, starting with the last bit, are set to one logical state (as described in the previous recalculation mode). This continues until the second bit trigger is set to a single state. In the subsequent recalculation cycle, under the action of the unit output potential of the element 4, the trigger 1.1 of the first discharge is set to one, and all other triggers are set to zero states. In 3 second operation modes of the counter. The subsequent cycles are similar to the described first cycle (see Table 6-10 in Fig. 3 for cases N 3-7). As can be seen from the table. 6-10, the repetition periods of code combinations in the counter's counter mode are determined by the expression T 2Nt. Among these code combinations, it is easy to establish codes 51111 with N 5 (Table 8). The remaining code combinations have similar configurations, but differ from each other in length (by the order of code combinations). Such an embodiment of the counter allows to significantly expand the functionality and scope of application by providing two modes of formation of code combinations. Claims of the Invention A functional counter containing N bits, each of which is made on a 1K flip-flop, the synchronizing input and the input of the zero setting are connected respectively to the clock bus and the zero setting bus, the first And element whose first input is connected to the direct output 1K -trigger second bit, of which 91 is characterized by the fact that, in order to expand the functionality and scope of application by obtaining an additional code sequence, a second AND element, a control bus and in each bit, cr Ome first, the OR element, the output of each of which is connected to the 1-input 1K-flip-flop of its bit, the first and second inputs of the OR elements of all the bits, except the last, are connected to the direct outputs of the 1K-flip-flops, respectively, the previous and next bits, The first and second inputs of the element OR of the last bit are connected respectively with the direct output of the IK trigger of the penultimate discharge and with the inverse output of the 1K trigger of the first discharge, the output and the second input of the first element AND are connected respectively with the 1 input of the 1K trigger of the first time A row and a control bus, the first input of the second element I is connected to the direct output of the second stage GK trigger, the second input of the second element I and the K inputs of the first and second discharge 1K triggers are connected to the direct output of the 1K trigger bit, the output of the second element And is connected to the K-inputs of 1K-flip-flops from the third to the last bit. Taf / Zfjv- JTaS / tifAf s) / UffJ 3,000 oa-, , OOPl O B / 1 f Zijt OOOlI 7 (7 // T P / Lt About SG ToS / t Sf. 7) Gaul If-fMtfi) roa o fie2