SU482014A1 - "Variable dividers frequency divider - Google Patents

Description

(54) FREQUENCY DIVIDER WITH VARIABLE RATIO Frequency divider with variable goat divide division (DCPD) contains sequentially connected shaper 1 square wave, first shaper 2 pulses, delay line 3 / additional forwarder 4 pulses, emitter surface. 6, between which control and jjxpflOM and the output of the first driver 2 pulses are turned on a scaler- consisting of sequentially switched on triggers 7, 8, 9, 10, llj, H trigger 1I, controlling the coincidence element 6, the second form The device has 13 pulses, the output of which is connected to the first input of the trigger 12 and to the controlled inputs of the devices 14, 15, 16, 17, 18, which specify the initial states of the triggers 7, 8, 9, 10, 11. The control inputs of the devices 14, 15, 16, 17, 18 are connected to the bit outputs of the former 19 of the binary code signals, and the outputs are connected to the separate inputs of three 3, 7, 8, 9, 10, 11 .: The frequency divider with a variable division factor (DDC) has two main A channel is direct, consisting of elements 1, 2, 3, 4, 5, 6, 13 and countable, consisting of elements i7, 8, 9, 1О, 11, 12, and feedback channels, with upstanding IFrom devices 14, 15, 16, 17, 18, respectively. A pulse sequence or sinusoidal voltage is applied to the PDCP input. FIG. 2, a, FIG. 3, o) some of which in the former 1 of the meander (see Fig. 2, b, fig. 3, p) and in the first former; 2 pulses are converted into a sequence of normalized pulses with the same repetition frequency (see Fig. 2, c, Fig. 3, p). This frequency in DPCD divisors 1, 2, 3, s in K times, where W 1, 2, 3, ... is the number of bits of the binary code, i.e., the output. DPKD passes each K-th pulse from the input sequence. M - RMB pulses are simultaneously supplied from the output of the first driver 2 pulses to delay line 3 and the input of the counting device, consisting of triggers 7, 8, 9, 10, 11. The number of triggers in the counting device (five as an example, In general, a per-counting device must contain J71 triggers. the pulses (figs 2, c), starting from the second after time 1, when the third bit of the binary code turned on and the division factor I became K - 5, are thrown over the trigger of the scaler. Timing diagrams of voltages at-i are given for trigger 7 on (Fig. 2, e), for trigger 8 on (Fig. 2, g). For trigger 9 on (Fig. 2, h), for trigger U on (Fig. 2, i) and for trigger 11 on (Fig. 2, d).:: .....,.:.: .. ...,. . By the time t point, all the triggers 7, 8, 9, .10, 11 of the device are each in the same state and impulse (the first after the moment of time. TV (see Fig. 2, c) sequentially moving - triggers 7, 8, 9, | 10, 11 in the second order (see. Fig. 2,: e, g, .3, - and, and.) At the same time, at the output, the triger 11 of the scaling device forms- trigger signal for trigger 12,: control element of coincidence 6, which flips trigger 12. The potential jump of the output of trigger 12 (see. Fig. 2, e) acts on the control input of coincidence element 6 to open It controls its input for the delayed in the delay line 3 at the time of the pulse that passes to the output of the coincidence element 6 (see Fig. 2, d, Fig. 3, c). Then the pulse through the second driver 13 pulses are passed to the PDKD output (see Fig. 2, e, Fig. 3, y), flips the trigger 12, which closes the coincidence element 6., i In addition, the impulse from the PDCD output, the passage through the open control, device inputs 14, 15, 17, 18 (see FIG. 2, l) and the device 16 (see Fig. 2, m), flips the triggers .7, .8, 9, Yu, 11 of the precalculation device to the initial states (see Fig. 2, g, g, 3, and and, fig. 3, f, x, c, h, u). Which are the initial ones for the start of a new counting of the counting device. The time diagram of voltages (see Fig. 2, k) shows the potential state of the outputs of devices 14, 15, 17, 18, and 2, n - output device 16, Through the K-th pulse from the output of DPCD not i passes to the corresponding separate inputs of the trigger 7, 8, 9, 1O, 11. Wrel-sh. the passage of the K-th pulse from the input of the delay line 3 to the output of the PDCD and the setting of the initial states of the triggers 7, 8, 9, 1O, 11 of the counting device is not. must exceed the time through which at the output of the first driver 2 pulses in: K + 1 pulse. . The work of the DPDC is illustrated by the time- BbiMH. voltage diagrams in FIG. 2 before the moment of time .t .. for cases K .1, and after the moment of time for cases. . . . . . . .To understand the need for the included delay line 3 in the DPCD, j time diagrams of the voltages in Fig. 3 are shown, which correspond to the time diagrams of the voltages of Fig 2 from the time of trt, but are shown in time (in

five times) the time scale to show the transients in the trigger 7, 8, 9, 10, 11 of the scaler, trigger 12.

At the division ratio, all pulses from the output of the first driver. 2 pulses are passed to the DPKD output. When this is done, each pulse that passed to the PDCD output passes through the devices 14, 15, 16, 17, 18 to the separate triggers. Gerovs 7, 8, 9, 1О, 11, respectively, and throws all the triggers of the counting device into such initial states that the subsequent pulse, which appeared at the output of the first driver 2 pulses, flips all the trigger- | 7, 8, 9, 10, 11 of the scaling device one after the other, throws the trigger 12 control and the match element 6, | opens the match element 6, itself pro. the second shaper 13 of tia pulses the DPCD output goes through it, flips trigger 12 again, closes matching element 6 and flips all triggers 7, 8, 9, 10, 11 of the sweeper, and so on.

Each device 14, 15, 16, 17, 18, which specifies the initial states of the corresponding triggers 7, 8, 9, 1 O, 11 of the counting device, is made in the form of two identical coincidence elements interconnected. The control input of the second coincidence element connected to the first match element in such a way that

(when the first element of the match is open, the second element of the match is closed and vice versa,,; ..; ...

Subject invention

A variable divider frequency divider containing the first pulse generator connected in series, the emitter follower, the coincidence element, the second pulse generator and the trigger controlling the matching element, the first input of which is connected to the output of the second pulse generator, and the output from the control input of the element coincidence, that is, with the aim that, in order to provide control of the division ratio by the binary code and TAKE it when the input voltage is of arbitrary form, the output the first pulse former; The INPUT of which is connected to the output of the meander mapper is connected to the input of the counting device on the series-connected triggers and the input of the delay line connected to the additional pulse shaper connected between the output of the delay line and the input of the emitter follower. Output of the counting device Connected to the second input of the control trigger, while the separate inputs of the trigger of the counting device are connected to the outputs of the devices that define the initial states of the triggers, the controlled inputs of which are connected to the output of the second pulse driver, and the control inputs are with binary outputs of the binary code driver.

FIG. 2