SU1105893A1 - Digital multiplying-dividing device - Google Patents

Description

The invention relates to computing, in particular, to special microprocessors. A digital multiplier divider device is known that contains a two-channel code-frequency converter, performed on two controlled frequency dividers fed by a reference pulse generator, two counters, a factor multiplier register, a two-code matching device, two valves and a control trigger, the counter inputs are connected to the corresponding two-channel outputs code-frequency converter through the valve whose control inputs are connected to the potential input of the control trigger, the zero input of which is connected to the output the coincidence devices, and the inputs of the latter are connected to the outputs of the register of the multiplier and to the inputs of one of the counters. The disadvantage of this device is the low speed and hardware redundancy. The speed is limited by the frequency of the reference frequency generator and a two-channel converter built on binary frequency multipliers. The closest to the proposed technical entity is a digital multiplier-separator device containing a controlled frequency divider, a counter, an element I, a result counter, the information inputs of the controlled frequency divider are connected respectively to the inputs of the first operand of the device output of the controlled frequency divider connected to the counting input of the counter (the setup inputs of which are connected respectively to the inputs of the second device's perandah, the output of the counter I is connected to the first input of the element, and you the stroke of which is connected to the control input of the controlled frequency divider, the outputs of the result counter are the outputs of the result of the device 21. The disadvantage of this device is also low speed. The aim of the invention is to increase the speed of the device. The goal is achieved by the digital splitter containing a controlled frequency divider, a counter, an ele ment, an And, a result counter, and the information inputs of a controlled frequency divider are connected respectively to the input day of the first operand of the device, the output of the controlled frequency divider is connected to the counting input of the counter, the installation inputs. Which are connected respectively to the inputs of the second operand of the device, the output of the counter is connected to the first input of the And element, the output of which is connected to the control input of the controlled frequency divider, the outputs of the result counter are the outputs of the result of the device, a controlled frequency generator is inserted, containing a controlled frequency divider, a group of delay elements and a comparison circuit, the bit The single outputs of the controlled frequency divider of the controlled oscillator-frequency are connected respectively to the inputs of the first group of the comparison circuit and through the group of delay elements respectively to the inputs of the second group of the comparison circuit, the output of which is connected to the second input of the And element, the output of which is connected to the control input of the controlled the frequency divider of the controlled frequency generator, the output of the controlled frequency divider of the controlled frequency generator is connected to the counting input of the result counter, and the information inputs are ineny respectively with the operand inputs of the third device. The drawing shows a functional diagram of the proposed device. The digital multiplying-dividing device consists of a controlled frequency divider 1, counter 2, counter 3 of the result, element 4,; controlled frequency generator 5 containing a circuit, comparison b, a group of delay elements 7 and a controlled frequency divider 8. In the initial state, the counters 2 and 3 are zeroed, And 4 is closed by a zero potential supplied to the control input from the counter 2. In the controlled dividers of frequencies 1 and 8 there are operands X and Y, at the inputs of the comparison circuit b there are equal codes. At the output of the comparison circuit, there is a single potential. With the inequality of the codes at the inputs of the comparison circuit 6, a zero potential appears at its output. The device begins to work after insertion of operand Z into counter 2, since a single potential appears at its output and element 4 opens. When the unit potential appears from dividers 1 and 8, one is subtracted. In the first and second inputs of the comparison circuit 6, the codes are not equal during the time determined by the group of delay elements 7. After the delay time, the potentials of the codes are compared, and the next pulse front is formed at the output of the comparison circuit (positive potential after generating a zero potential during the delay time) . From parts 1 and 8, the next unit is subtracted. Changing the code in divider 8 leads to the generation at the output of the comparison circuit b of the next pulse, i.e. at the output of the controlled oscillator 5, the frequency of the pulsator is generated, and it can be named VT7-3 o

At the outputs of dividers i and 8, pulses with a frequency corresponding to BGHHO

F.

Frequency Fg enters the 3 result counters for the time G 1 / F, required 1105893

datum to read the number from the meter whose frequency

d- 2 Z. 7G

in the counter s for time G, g 4 fic FV,

number is drawn; p8%

The proposed device allows to increase the speed in comparison with the prototype.

Claims (1)

A DIGITAL MULTIPLE DIVISION DEVICE containing a controlled frequency divider, counter, element And, a result counter, wherein the information inputs of the controlled frequency divider are connected respectively to the inputs of the first operand of the device, the output of the controlled frequency divider is connected to the counter input of the counter, the installation inputs of which are connected respectively to the inputs the second operand of the device, the output of the counter is connected to the first input of the AND element, the output of which is connected to the control input of the controlled divider h the frequencies, the outputs of the result counter are the outputs of the device, characterized in that in order to improve performance, a controlled frequency generator is introduced into it, containing a controlled frequency divider, a group of delay elements and a comparison circuit, and the discharge outputs of the controlled frequency generator are connected respectively to the inputs the first group of the comparison circuit and through the group of delay elements, respectively, with the inputs of the second group of the comparison circuit, the output of which is connected to the second input of the element And, you orogo 'is connected to the control input of the frequency divider managed f / Y managed frequency generator, you are a _ _and stroke managed frequency divider (m · managed oscillator coe-'Ί union of the counter with a counting input PE 2 result, and data inputs soe-' * I are dinen respectively with the inputs of tertv ‘of its device operand. Si 00 with FD