SU603109A1 - Pulse stretcher - Google Patents

Description

The invention relates to the field of computer technology, namely, to the formation of pulses with interference suppression. A known discrimination and delay pulse scheme, comprising two triggers, controllable counters, a mono-oscillation circuit, and logic elements, in which an output impulse is generated for the duration of the control signal that exceeds a specified value. equal to the duration with a given time delay 111 However, such a circuit is rather complicated, and the duration of the output pulse varies depending on the duration of the control signal. Also known is a pulse sweeper, containing two flip-flops and two stop lines, having a constant output pulse width, determined by a delay line, and the output pulse is not fragmented 2. Such a pulse sweeper is that a short-term disturbance causes the output flip-flop and issuing a false output pulse. The object of the invention is to increase the noise immunity at the control input of the first trigger. The circuit is achieved by the fact that a pulse extender containing a clock pulse generator and a serially connected first trigger, a delay unit and a second trigger, the unit input of which is connected to the zero input of the first trigger, is additionally introduced a delay unit, the first and second inputs of which are connected to the unit output of the second trigger, and the output of the additional delay unit is connected to the zero setting and the counting input of the second trigger, with the second in ∞ of the first power block connected to the control input of the first ggera and third inputs of delay units connected to the output of the clock. FIG. 1 shows a functional diagram of the proposed pulse remover; FIG. 2 - time diagram of his work.

The expander And (pulses contains the first trigger 1, the output trigger 2, the delay block, an additional delay block 4 containing the trigger 5 of the first delay device, circuit 6; the counter "7 and the decoder 8 are contained in the edercke 3 block.

The control signal arrives at 8, the clock pulses go to terminal 1O, terminal 11 is the initial start terminal, and the output is removed from terminal 12.

In the initial state at terminal 0, the left control signal arriving at the single input (3 "input) jg Gera 1, sets at its output 13 a single signal, which is fed to the installation input 1 (3 - one) of the trigger 5, which however, it cannot be switched until its zero input 14 (I - input) is a zero signal. At the exit 15 of the trigger S-zero zero, | prohibiting the operation of the circuit AND 6, at output 16 of which there is a single signal received at zero input 17 (T input) of trigger 1 and eD-at input 19 (& input) of trigger 2. Triggers 1 and 2 of this swap are not cross, so as triggers i, 2, 5 to the trigger {input in counter 7, are set to zero by the zero input on the ii input) and the state, and by the unit HKHHoivQr in the NW heading-on input) the initial state on terminal 11 "left skgnv 1 that {enters the zero input 19 (ti - input}, r | rigger 2, after setting the beer to the output but luneMMelU zero signal, It arrives at the 2O input of the & gk (3 - input) counter 7, and the zero input 21. THE 8TH counter (the inputs of the flip-flops entering the counter 7 connect you to each other JJQ.) At the output 22 of the decoder 8 - the zero signal , the input and synchronization input 23 (from the input) to input 24 of the installation of Trigger 2, After a single signal is applied to terminal 11, the expander is ready for operation and retains its original state until the arrival of a single control signal, since. This is affected only by clock pulses, which are fed to the input 25 of the installation / 5 ° O and the synchronizing input 26 of the trigger 5, which is not. can switch, since at its zero input 14 there is a zero signal. In addition to ETOEE, the clock pulses appear at the clock input 27 j5 of the counter 7. Since the zero signal at the input 21 of the counter 7 is zero, the counter 7 also cannot switch,

After a single driving signal is applied to KneMsiy 8, trigger 1 remains

in the single state, and the trigger 5 by. the decay / first passed clock pulse switches to one state, and the next clock pulse passes through AND circuit 6 - at output 16, a zero signal which sets input 1 to trigger 1 to zero state. By dropping the same second clock pulse, a trigger of 5 g is switched to the zero state, and subsequent clock pulses confirm this state of the trigger 5 before the control signal ends (on terminal 9, zero ciirHan). The zero signal at terminal 9 switches trigger 1 to one state and confirms the / - nupevye-to-state trigger 5. The zero signal at output 16 sets input 18 of trigger 2 to the power condition - at terminal 12 a single signal 6 appears. After the counting of a predetermined number of pulses, the output of the counter 22 produces a positive pulse 22 which, on decay of which, the trigger 2 switches to the zero state, and the zero signal on terminal 12 sets the initial state of the counter 7. After that, the expander vmpuysov odits in the initial state.

If the pulse expander is in its initial state, the interference is shown as shown in FIG. 2 in the form of a pulse 28, the following occurs: a single interference signal enables switching of the trigger S, and according to the decay of the first passed clock pulse, this switching is iiipobcxoAHT. Since the mold does not start output 16 on the front of the next clock pulse, if there is a single signal at output 15, the following conclusion can be made if the duration of the control signal is less than; the length of the segment is 29, then the output Ym11uns will not be issued. This means that Sch} just the expander does not provide the output from interference {(the output is less than the length 29,

In Fig. 2 from) bus 30 shows the maximum delay of the output pulse relative to the controlling one, and this means that if the duration of the control of the shift of the signal is greater than the interval 30, then it is provided; reliable reception of the control signal.

Claims (2)

Therefore, with a particular use of the pulse expander, a period of clock pulses is chosen in order to ensure reliable reception of pulses and the suppression of the maximum duration of the interference. An inventive extender nmpup-jv, comprising a clock pulse generator and successively connected first trigger, a delay unit and a second trigger whose single input is connected to the zero input of the first trigger, characterized in that with an up-circuit & amplifier circuit across the control input of the first trigger it additionally introduces a delay unit, the first and the first which inputs are connected to the unit output of the second trigger, and the output of the additional delay unit is connected to the zero setting and the counting input to second trigger, the second input of the first Delay unit is connected to the control input of the first trigger, and the third inputs of the delay blocks are connected to the output of the clock generator. Sources of information taken into account in the examination: 1.UK patent number 1298420 Cl. H 3 P, l972. 2. USSR author's certificate number 429518, cl. H 03 K 5 / O4. 1972. 22