SU930614A1 - Pulse synchronizing device - Google Patents

Description

The invention relates to a pulse technique and can be used to temporarily tie pulses in automation and computing devices that exchange information asynchronously. A device for synchronizing pulses is known, which contains an input trigger, an OR element, a trigger built on AND-NOT elements, two AND elements and a counting trigger I. The known device makes it possible to generate paired synchronized pulses Llj in time. The disadvantage of the device is that it can generate spurious pulses if the duration of the input asynchronous i ipulse exceeds the duration of the synchronizing pulse. This is due to the fact that at the end of the second synchronized pulse Pulse device returns to its original state, i.e., At the output of the input and counting triggers, a potential O is established, but present at the device input, as well as at the installation input of the counting trigger, the synchronized pulse switches the input trigger again, and potential 1 is set at its output. This allows the device, regardless of the number received at the counting input trigger of synchronized pulses shaper false pulses as synchronization pulses arrive during the entire time the input asynchronous pulse is present at the course of the device. The closest in technical essence to the invention is a device, soda | Each input trigger, an OR element, a trigger executed on AND-NOT elements, three AND elements and a trigger with a counting input 2. In this device, the outputs can also receive not one but several pulses in the case. 39 if the duration of the synchronized pulses will exceed the duration of the synchronizing pulses. This is due to the fact that at the end of the second synchronized pulse, the device returns to its original state, i.e. At the output of the input and counting triggers, a potential O is established, which is not present at the device input, and the synchronizing pulse again switches the input trigger at the installation input of the counting trigger, and potential 1 is set at its output. This allows the device, regardless of the number received at the counting input counting trigger of synchronized pulses to generate spurious pulses as the synchronizing pulses arrive during the whole time of the presence of the input asynchronous pulse at the input de device. The purpose of the invention is to increase the reliability due to the formation of synchronized output pulses for any duration of input asynchronous pulses. This goal is achieved by the fact that a pulse synchronization device containing an input bus and subsequently connected to the first trigger, the OR element, the second trigger executed on the AND-NES elements, the first AND element, the second AND element and the first output bus, as well as sequentially connected third trigger, tre-. The And element and the second output bus are also connected to one of the inputs of the first trigger, while the second input of the second element And is connected to the second output of the third trigger, and the second input of the third element And is connected to the second input of the OR element and the output of the first And element, the second input which is connected to the second input of the second trigger and clock bus, additionally introduced the element AND the element OR NOT, one of the inputs of which is connected to the output of the element OR, and the other connected to the input bus and the first input olnitelnogo AND gate, the output and second input coupled respectively to the second input of the first flip-flop and the second output of the third flip-flop, one of whose inputs is connected to the output of the second AND gate and the other connected to the output of OR-NO. li-4 The drawing shows the functional diagram of the device and the device for synchronizing pulses contains the first trigger 1, additional element AND 2, input bus 3 element OR NOT C, third trigger 5, second element AND 6, third element And 7, first element AND 8, evil AND 8, the element OR 9, the second trigger performed on the elements AND-NOT 10 and 11, the bus 12 clock pulses, output tires 13 and 14. The single input of the trigger 1 is connected to the output of the element And 2, the first input of which is connected with input bus-bar 3 input pulses and one of the inputs of the element OR- NOT k, the zero input of the trigger 1 is connected to the output bus 14 of the device and the output of the element And 7, and the output of the trigger 1 is connected to the first input of the element OR 9, the second input of which is connected to one of the inputs of the elements And 6 and 7 and the output of the element And 8. The first input of the trigger performed on the elements AND-NOT 10 and 11 is connected to the output of the element OR 9 and connected to another input of the element OR-NOT 4, the second input of this trigger is connected to the bus 12 clock pulses and the second input of the element And 8, the first input of which connected to the output of the element AND NOT 11 and the second input element AND-NOT 10, the output of which is connected to the second input of the element AND-NOT 11. The counting input of the trigger 5 is connected to the output bus 13 of the device and the output of the element AND 6, and the setup input to the output of the element OR-NOT 4, the single output of the trigger 5 connected to the first input element And 7; and zero - with the second input element And 6 and the second input element And 2. The device operates as follows. In the initial state, the triggers 1 and 5 are in the zero state. Zero potential from a single output of trigger 1 is fed to the first input of the element OR E-Single potential from the zero output of the counting trigger 5 is fed to the second input of the element AND 6 and the second input of the element 2, and the zero potential from the single output to the first input of the element And 7Input Asynchronous pulses are received from bus 3 through an AND 2 element at a single input of trigger 1 and put it into a single state. Potential 1 from a single output of trigger 1 through the element OR 9 is fed to the first input of the element AND-NOT 10. In the absence of a synchronizing pulse on the bus 12, the output of the element AND-HE 11 contains potential 1, which is fed to the second input of the element, meyt 1 - NOT 10 and the first input element AND 8. In this case, the output of the element AND-NOT 10 is set to the potential of a logical zero, which locks the first input element AND-NOT 11, the output of which sets potential 1 regardless of the potential level at its second input, those. on the bus 12 device. The potential of the logical unit at the output of the element AND-NOT 11 is fed to the second input of the element AND-NOT 10 and the first input of the element 8. The first synchronizing impulse then arrives on the bus 12 through the open elements 8 and 8 and passes to the first 1-way bus. 13, the device and the counting input of the trigger 5 ac of the output of the element AND 8 also pass to the first input of the element NAND 10 through the element OR 9. At the end of the first synchronizing pulse, the potential O appears on the bus 13 and 13 a single output of the trigger 5 sets the potential 1, which arrives at the first input of the element And 7. With the zero output of the trigger 5, the potential O arrives at the second input of the element 6, prohibiting the re-issuance of a normal pulse to the bus 13, to the second input of the element 2, prohibit repeated trigger trigger 1 n issuing a second pulse follows.

A second synchronization pulse arriving on bus 12 then through open elements AND 8 and AND 7 passes to the second output bus 1 of the devices and the zero input of the trigger 1, and from the output of the element AND 8 through the element OR 9 to the first input of the element AND-NOT 10 and one of the inputs of the element OR NOT 4. In this case, the trigger 1 is set to the initial zero state and from the output of this trigger the potential O arrives at the first input of the element OR 9 at whose output the potential 1 will be present at the second input during the clock pulse . X

At the end of the second clock pulse at the output of the element And 8 and the tire on the Wits potential O

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which is also set at the output of the element OR 9When a third and subsequent clock pulses arrive at the bus 12 at the output of the AND 8 element and buses 13 and 1, the output pulses are not in TC. After issuing the second synchronized pulse, the trigger 5 will remain in one state and

10 will remain in this state as long as an input pulse is present on the bus 3- After removing the input pulse and issuing two synchronized pulses

15 at the output of the element OR-NOT k on Vits potential 1, which sets the trigger 5 to the initial state. In this case, from the zero output of the trigger 5, the potential 1 is fed to the second

20 input element And 2 and allows the new input pulse to pass through the element And 2 to a single input trigger 1 to form the next pair of synchronized pulses.

25 This device is not critical to the duration of the input pulse. This follows from the fact that after issuing output pulses, when the input pulse is not yet finished, the counting signal 3 ger 5 can be set to the original

the zero state only then, when, yes, its installation input will receive a high level from the output of the element OR NOT 4, i.e. Potentials must be present at its inputs Oh what

35 is impossible only after the end of the input pulse and the output of the output pulses. Thus, this mouth. The stability steadily forms two synchronized pulses independently

40 of the duration of the input asynchronous pulse, which increases the reliability of the device.

45

Claims (2)

1. USSR author's certificate number 55838it, cl. H 03 K 5/00, 1976, 2. USSR author's certificate number 632069, cl. H 03 K 5/00, 1977. J efJ