SU824124A1 - Time interval forming device - Google Patents

Description

(54) DEVICE FOR FORMING TEMPORARY INTERVALS

I

The invention relates to computer technology, in particular to the automation of technological processes, and can be used in automated control systems for the formation of single consecutive intervals and the delivery of information in current time.

A device for generating time intervals is known, comprising a reference frequency generator, the output of which is connected to the counting input of a frequency divider, a matching element, a trigger trigger, a trigger device, and a scale 1 register.

The disadvantage of the device is the complexity of the device, a significant amount of equipment.

Closest to the proposed technical entity is a device for forming time intervals, containing a reference frequency generator, an output connected to the input of a frequency divider, the first outputs of which are connected to the first inputs of the switch, an output connected to the first input of a time counter, the second input to the output of the first register, and the third input - with the trigger output, the first input of which is connected to the output of the time interval counter and the first output of the device 2.

However, this device has limited functionality due to the lack of interfacing with the input-output channel of the electronic computing machine and the possibility of issuing data on the current time.

The purpose of the invention is to extend the functionality of the device.

The goal is achieved by the fact that three registers are entered into the device, a current time counter and a decipher, the first output of which is connected to the input of the first register, the second output to the first input of the current time counter, the second input of which is connected to the second output of the divider and through the second register - to the second output of the device, the second input of the second register is connected to the output of the current time counter, the third input is connected to the third

0 by the output of the descrambler, the first input of which through the third register is connected to the first input of the device, the second input - to the second input of the device, and the fourth output -

with the second input of the trigger and the second input of the time interval counter, the third input of which is connected to the third input of the device through the fourth register.

The drawing shows the scheme of the device.

The device contains a generator 1 reference frequency, divider 2 frequencies, nerve scale register 3, switch 4, counter 5 time slots, output 6, trigger trigger 7, input data buses 8, fourth register 9, address buses 10, third register AND addresses, decoder 12, tracking bus 13, current time counter 14, second register 15, data output buses 16.

The generator 1 of the reference frequency is connected to the counting input of the divider 2 frequencies, the outputs E, ... Fr, KOTOporo are connected to the information inputs of the switch 4, and the output FH is connected to the counting input of the counter 14 of its current time and the synchronization input-register 15, whose outputs are output data buses 16. The input data buses 8 through the data register 9 are connected to the information inputs of the counter 5, the output of which is the output of the device 6 and is connected to the second input of the trigger 7. Address buses 10 through the address register 11 are connected to the information inputs of the decoder 12, the gating input of which is connected to the tracking bus 13. The first output of the decoder 12 is connected to the installation input of the time interval counter 5 and the first input of the start trigger 7, the output of which is connected to the gate input of the switch 4, the installation inputs of which are connected to the second output of the decoder 12, the third output of which is connected to the installation input counter 14 current time, the outputs of which are connected to the information inputs of the buffer register 15, the sampling input of which is connected to the fourth output of the decoder 12.

The device works as follows. After the address code 10 is written to the address bus 10 in the register 11, a signal appears on the bus 13 of the trail enabling the decryption of data from the address register 11 to the information input of the decoder 12.

Depending on the address code, the decoder 12 generates the following control signals: the resolution of the recording in the counter of 5 time intervals of the code of the time interval received on the input data buses 8 through the data register 9 with simultaneous installation of the trigger in a defined state: , the enable signal of the sample of the current time code from the buffer register 15, the reset signal containing the current time counter 14.

The formation of the time interval is as follows.

On a signal from the decoder 12, the trigger 7 is set to a state in which the passage of one

from the frequencies F. | ... F to the output of the switch 4, in accordance with the register code. At the same time, the code of the time interval arriving at the input data 8 by means of the data register 9 is entered into the counter 5.

The pulse generator 1 of the reference frequency Fj is fed to the counting input of a frequency divider, at the outputs of which frequency signals are generated that are associated with the reference frequency by the following relations

f :: .-.

p1re

- (

where A is the discreteness of the grid of frequencies removed from the divider.

The signal of the end of the time interval generated at the output 6 of the device is fed to the second input of the trigger 7. In this case, the trigger is set to the state in which the output of the signal appears at its output, prohibiting the operation of the switch 4.

The time interval t generated at output 6 is defined as follows.

t TQ-M -A,

where is TO

P - the contents of the register 3 scale;

M - the contents of the counter 5.

The issuance of data on the current time is as follows.

At the beginning of the operation, the signal from the output of address sender 12 to 0, the installation input of the current time counter 14, the contents of the latter is zeroed out. Pulses with frequency FK from the output of divider 2 frequencies are fed to the counting input of the current time counter 14 and the synchronization input of the buffer register 15, into which data arriving at its information inputs from the counter output of 14 time slots are entered. When a signal is sent from the output of the decimator 12 to the sample input of the buffer register 15, the current time code 0 appears on the output data 16.

The time interval within which the current time is fixed is determined as follows.

. Go2

S where TO is the p-resolution of the younger time series of the code of the current time; M is the data output width.

Entering into the proposed device the data register, address register, decoder, current time counter, buffer register expands the functionality of the device.

Claims (2)

1. USSR author's certificate number 434401, cl. G 04 F 10/04, 1972. 2. USSR author's certificate 0 No. 577509, cl. G 04 F 11/04, H 03 K 5/00, 1976 (prototype).