SU1439573A2 - Number comparator - Google Patents

Abstract

The invention relates to computing, can be used as a device for pre-appraisal when implementing technical means of discrete automation and computing and is an improvement of the device according to ed. USSR 1285461. The purpose of the invention is to increase the reliability of the results of comparison with the calculation of the permissible error with a change in tolerance depending on the magnitude of the compared numbers. The device for comparing numbers contains AND-NE elements 1, 2, 11, 21, AND-IPI elements 3, 4, element NOT 5, triggers 6-10, 19, shift register 20. Shift register 20, the information is fed to the information inputs Trigger 9, designed to set the register 20 in the mode of parallel recording of input information or in the mode of information in the sequential code on the signal from the element AND-NOT 21, fixing the occurrence of the unit in the high bit one from comp Vai numbers 1 yl. (L

Description

17

N)

t

The invention relates to computing technology, can be used as a device for admissible evaluation when implementing technical means of discrete automatics and computing equipment, and by improving the device according to the author. ff 1285461.

The purpose of the invention is to increase the reliability of the results of comparing codes of numbers with allowance for permissible error with a change in tolerance depending on the value of comparison of numbers.

The drawing shows a structat ™ on the device diagram.

The device for comparing the numbers contains the elements AND-NOT 1 and 2, the elements AND-MLI 3 and 4, the element NOT 5, the trigger 6-10, the element AND-NOT 11, the inputs 12-15 of the compared numbers, the input 16 specifying the error, clock input 17, input 18 of the initial setup trigger 19, the shift register 20 and the element AND NOT 21.

The device works as follows:

A valid difference is compared to the number of numbers given in the form

„B

where L is the value of the first most significant bit, equal to 1, in any of the compared numbers, n K O, 1,2 is the number 1 in the younger bits of the shift register 20, determining the allowable error; n - the degree of the number 2, determined the absolute reliability of this pair of numbers.

In this case, the following results of comparing numbers are possible; after fixing the first incomparability with A B, the difference of the compared numbers is always 2 1

or several subsequent stargai bits, including all bits.

exceeds if in any one

aiibjs, k does not exceed the value

2

,, if a; B ;.

Before starting work, input 18 35 of the initial installation of the device to the inputs of the installation in O from the first to the sixth flip-flops 6-10, 19 and the shift register 20 (with parallel recording and sequential output) receives the installation signal, with both direct and inverse The outputs of the flip-flops 6-10, 19 are set to zero and single signals, respectively. From the input 16 of the error setting, the information inputs of the shift register 20 receive a parallel code corresponding to the specified tolerance. At the same time, from the output of the first senior bit of register 20 to the fifth

O and L- also differs in the sixth inputs of the installation in 1 of the I tracks, similarly, when the difference is five of the first 6 to the second 7 of the flip-flops, a single level signal arrives and through the NOT 5 element locks the second inputs of the second 55

a: different from

11; |||

I J of compared numbers always exceeds

2

fTj- if in one any or several- 2k

yolmih later senior bits, including all K-e, a; differs from 1, and b; differs from the difference of the compared numbers not exceeding the levels of 1 of the fourth 9 and of that 10 triggers.

From the clock input 17 of the device to the synchronization inputs of the triggers

five

Q

$

0

em - at A B or at B, if

after fixing the first incomparability, as a result of comparing the higher order bits, comparing the number of numbers, including all K-e bits, the difference in numbers was not exceeded

values younger bits

compared numbers from zero to n1 are |

at A Bj, if, after fixing the first incomparability, when comparing the remaining most significant bits, including all the bits, the difference between the numbers of the numbers was not exceeded

2

 but the first incomparison was recorded in the lower bits from n-1 to zero, the difference of the compared

numbers exceeds - “ij- under the condition

2

ab; and does not exceed xij; He provided a “c b; five

similarly, when A B is the difference chi

2

the village exceeds the value --- R- at the first incomparison in the lowest bits

0

from p-1 to zero under conditions if

aiibjs, k does not exceed the value

2

,, if a; B ;.

Before starting work, input 18 5 of the initial installation of the device to the inputs of the installation in O from the first to the sixth flip-flops 6-10, 19 and the shift register 20 (with parallel recording and sequential output) receives the installation signal, with both direct and inverse The outputs of the flip-flops 6-10, 19 are set to zero and single signals, respectively. From the input 16 of the error setting, the information inputs of the shift register 20 receive a parallel code corresponding to the specified tolerance. At the same time, from the output of the first senior bit of register 20 to the fifth

8 of the first 6 in the second 7 triggers receives a signal of a single level and through the element HE 5, the zero level blocks the second inputs of the

In the fourth quarter of the 9th and of that 10 triggers.

From the clock input 17 of the device to the synchronization inputs of the triggers

6-10, 19 and register 20 receive clock pulses.

From the first 12 and third 15 inputs of the device numbers being compared, respectively, the first inputs of the first 1 and second 2 elements of the NAND are synchronously received in the binary number system in the sequential code by the leading bits in the forward and inverse form, respectively, the first compared number.

The second inputs of the first 1 and second 2 elements NAND and the first and second inputs of the element NINA 21 from the second 13 and fourth 14 inputs of the compared numbers of the device in inverse and direct form, respectively, arrive in synchronism with the first the second compared number. The inverse values of the first and second numbers from inputs 15 and 12 are fed to the inputs of the AND-NOT element 21.

When appearing at the first or second inputs of an AND-HE element 21 of the value O, a signal 1 appears at the output of the element IS-NOT 21, which arrives at the first input of the sixth trigger 19, and the signal at the first input of the register 20 arrives from the output of the sixth 19 trigger.

When signal 1 arrives at the first input of register 20, the shift of the recorded information begins.

At the direct outputs of the first 1 and second 2 elements, the NAND defines the first, non-zero difference of the higher bits of the compared numbers

The result of the first non-comparison of the bits of the numbers A B is formed as a signal 1 at the direct output of the first AND-NO element 1 and the result r A B - at the direct output of the second element IS-NOT 2o A single signal at A B is fed to the first input of the installation at t the first trigger 6 and the first inputs of the first 3 and second 4 elements I-IPI. In the case of a single signal arrives at the first input of the setup in 1 second 7 trigger and on the first inputs of the second AND elements of the first 3 and second 4 I-OR elements In the case of a clock pulse coming from the clock input 17 of the device, on the forward and inverse outputs of the first trigger 6 will set the single and zero signals respectively. In this case, the zero signal from the inverse output of the first trigger 6 is blocked by a second

The first input is set to 1 of the second flip-flop 7, the Single signal from the direct output of the first flip-flop 6 is fed to the second inputs of the first and second elements of the first 3 and second 4 I-ShSh elements and the third input of the third 8 of the trigger, respectively.

Similarly, with a clock pulse, the direct and inverse outputs of the second flip-flop 7 are set to single and zero signals, respectively. In this case, the first signal from the inverse output of the second trigger 7 blocks the second input of installation B 1 of the first trigger 6. A single signal from the direct output of the second trigger 7 goes to the fourth input of installation to 1 of the third trigger 8 and the second inputs of the second and. The first elements are AND the first 3 and the second 4 elements are AND-OR.

In the case of any difference of each subsequent low bit of the number A from O, and the number B from 1

0

five

0

five

0

five

gives the difference of the compared numbers

72, where m is the number of the digit of the number, starting with the youngest. Similarly, for any difference in any subsequent bit of the number A from 1, and the number B from O gives the difference of the compared numbers 2, where m is the number of the digit of the number, starting with the youngest.

When AB is fixed, any difference in subsequent bits higher than n - 1 of A from O, and of B from 1 leads to the appearance of a single signal at the inverse output of the second AND – NE 2 element supplied to the second input of the 1st trigger of 1 8. The presence of single-level signals from the input 16 of the device error setting, from the direct output of the first trigger 6 and from the inverse output of the second element, AND-NOT 2 translates into a single, third state of the trigger 8, a signal; from the inverse output of which is fed to the first input of the element AND-NOT 11, the output of which establishes a single signal corresponding to the difference between the difference of the c2: numbered numbers and the value of j

Similarly, when A «iB, any difference in the number A from 1, and the number B from O results in the appearance of a single level signal at the inverse output of the first element AE AND – NE 1, which in combination with the unit level signals from the direct output of the second trigger 7 and input 16 setting the error of the device ensures the presence of unit levels on the first, fourth and fifth inputs of the installation in 1 of the third trigger 8 "At the inverse output of the third trigger 8, a zero level is set, and at the output of the device a single, determining the difference exceeding Vai numbers on the margin

The time of the compared low-order bits of the compared numbers from n-1 to zero at the output of register 20 establishes a zero signal that goes to the fifth and sixth inputs of the installation in 1 of the third trigger 8 and the third entry of the installation in 1 of the first 6 and second 7 triggers and blocks them. At the same time, the zero signal from the output of register 20 is fed to the input of the HE 5 element, the output of which establishes a single signal that is fed to the second inputs of the fourth 9 and fifth 10 flip-flops. In the next comparison of the lower digits of the numbers being compared, c, a / b; where i varies from n-1 to O, at the direct output of the first element AND-NOT 1 a single signal is set, which is fed to the second inputs of the first element of the AND 3 elements of the first 3 and second 4 elements of the ISH and sets a single signal at its output o The clock pulse from the device input 17 on the inverse output of the first trigger 10 sets a zero signal, which is fed to the second input of the AND-NE element 11, the output of which sets a single signal corresponding to the difference between the compared ch2 villages of "Е

If in the next comparison, the youngest bit is a; b ;, the unit signal is set at the direct output of the second element AND-NOT 2 and is fed to the first inputs of the second AND elements of the first 3 and second 4 AND-OR elements, and the output signal of the second element AND-OR 4 sets a single signal arrives at the first input of the fourth trigger 9, on the inverse output of which

clock signal Eulsu from the input 17 of the device is set to zero signal, which is fed to the third inputs of the elements AND of the first element ICH SHI 3 and blocks further operation of the circuit, which corresponds to the impossibility of exceeding the difference by comparison

21

nimac of the numbers of

unreasonable inability to:

signal output device. Similarly, in the case of AB, if, when comparing lower-order bits, compare Bets are numbered, starting with n-t, a. bj, at the forward output of the second NAND is set a single signal that is fed to. first entrances of the first elements of the first 3

0 and the second 4 elements I-11PI and sets a single signal at its output.

According to the clock pulse from the input 17. 5, the device at the inverse of the output of the first flip-flop 10 sets a zero signal, which goes to the second input of the AND-NOT element. At the same time, the signal 1 is set at the output of the device

0

that corresponds to the difference between the numbers compared

value -. If at the next

comparing the low-order bits a, - b, the direct output of the first element AND-NOT 1 is set to €; the single signal that arrives at the first inputs of the first elements AND of the first 3 and second 4 elements AND-OR, at the E output of the second element I-ШШ 4 establishes a single signal that arrives at the first turn of the fourth, trigger 9 According to a clock pulse at the inverse output of the fourth trigger 9, a zero sign is set.

five

0

The cash that arrives at the third inputs of the AND elements of the first element of the I-IPI 3 blocks the further operation of the circuit, which corresponds to the impossibility of transcending the difference c2

numbered values and, accordingly, the signal at the output of the device

55

Claims (1)

Invention Formula The device dll compare the numbers on the author, no. 1285461, about the fact that, in order to increase the reliability of the comparison results taking into account the permissible error with the change in tolerance depending on the value of the compared numbers, the device is entered the shift register, the sixth trigger and the fourth NAND element, and the inputs for setting the device errors are connected to the information inputs of the shift register, the synchronization and installation inputs in O of which are but connected to the clock inputs and inputs of the initial installation of all the triggers, the control input of the shift register is connected to the direct output of the sixth trigger, whose information input is connected to the output of the fourth AND-NOT element, the inputs of which are connected to the second input of the first and first inputs the second element NAND, the output of the high bit of the shift register is connected to the input of the element NOT,