SU1191919A1 - Device for statistical analyzing of random numbers - Google Patents

Abstract

A DEVICE FOR STATISTICAL ANALYSIS OF CASE HIGHS NUMBERS containing the tolerance register, X comparison circuit, subtractive counter and N analysis channels (, 2 ,, ...), each of which, except the last one, contains a comparison circuit, register, counter and the first and the second And elements, the output of the first And element in each of the (N-1) analysis channels is connected to the summing input of the counter of its channel, the first inputs of the first and second elements And in each of the (N-1) analysis channels are combined and connected to the output of the circuit compare your channel, the first group of inputs In each of the (N-1) analysis channels, respectively, are connected to the output group of the registers of the own channel, and the second groups of inputs of the comparison circuits of all (N-1) analysis channels are combined and form a group of information inputs of the device, the Nth analysis channel contains a counter, This is due to the fact that, in order to improve accuracy by controlling the parameters of random numbers, additional OR elements are introduced, four AND elements, and the third one in each of the (N-1) analysis channels. the AND element, the first and second OR elements and the trigger, and in The analysis channel has a trigger and an OR element, with the first and second outputs of the trigger in each of the (N-1) analysis channels connected to the second inputs of the first and second elements AND of their own channel, the third inputs of the first and second elements AND all (N-1 a) the analysis channels and the channel counter are combined and connected to the output of the first additional element I, the second input of which is combined with. the first input of the second additional element I and is connected to the clock input of the device, the second input of the first additional element (A component element I is connected to the first output of the N-ro trigger of the analysis channel, the trigger input of the N-ro channel is connected to the output of the OR element of the analysis channel, inputs which are connected respectively to the outputs of the counter of its channel, the second output of the N-ro trigger of the analysis channel is connected to the second input of the second and the first inputs of the third and fourth additional elements And, the third input of the second additional element I is connected to the direct output of an additional CM element, the inverse output of which is connected to the second inputs of the third and fourth additional elements I, the third inputs of which are connected respectively to the first and second outputs of the comparison circuit, the first group of inputs of which is connected respectively to the output group of the tolerance register, and the second group of inputs of the comparison circuit is connected to the group of outputs of the subtractive

Description

a counter whose input is combined with the first inputs of the third AND elements (N-1) of the analysis channels and connected to the output of the second additional AND element, the second input of the third AND element and the direct output of the first OR element in each H3 (Nl) analysis channels are combined and connected to the corresponding input of the additional element OR, the output of the second element AND in each of (I-1) analysis channels is connected to the first input

1919

the second control OR of its channel, the output of which is connected to the subtractive input of the counter of its channel, the output of which is connected respectively to the inputs of the second element OR of its channel, the inverse output of which in each of the (N-1) analyte channels is connected to the input of the trigger of its channel, and the output of the third element AND in each of the (N-1) analysis channels is connected to the second input of the second element or its own analysis channel.

one

The invention relates to computing and can be used for hardware determination of statistical random processes, for statistical analysis of a sequence of random numbers, as well as for monitoring and measuring the parameters of sensors of random numbers.

The purpose of the invention is to increase accuracy by controlling the parameters of random numbers, determining the statistical characteristics of random processes and forming integral histograms,

The drawing shows the block diagram of the device.

The device contains a register of 1 interval boundaries, a register of 2 tolerances, a comparison circuit 3, a comparison circuit 4 of N counters 5 inverse ordinates, a subtractive counter 6, elements AND 7, 8, and 9, elements OR 10 and 11, N triggers 12, four elements AND 13 -16,. Inputs 17 and 18 and outputs 19 and 20 of the device.

The information inputs 17 of the device are connected to the first inputs (N-1) of the comparison circuit 3, the second inputs of the i-th comparison circuit 3 (, 2, ..., N-1) are connected to the bit outputs of the i-ro register 1, output i th circuit 3 is connected to the first inputs of the ix elements And 7 and 8 of the first and. the second group, the output of the i-ro element And 8 of the second group is connected to the summing input of the i-ro counter 5.

The clock input 18 of the device is connected to the first inputs of the first and

The second elements And 13 and 14, the output of the first element And 13 is connected to the input of the Nth counter 5 and to the second inputs of the elements And 7 and 8 of the first and second-5th groups, the third inputs of the i-th elements And 7 and 8 of the first and the second group is connected to the corresponding outputs of the i-ro trigger 12, the output of the i-ro element And 7 of the first group is connected

0 with the first input of the i-ro element OR P of the second group, the output of which is connected to the subtractive input of the i-ro counter 5, and the second input - to the output of the i-ro element AND 9 of the third group,

5 bit outputs of the k-ro counter 5 (, 2, ..., N) are connected to the corresponding inputs of the k-ro element OR 10 of the first group, the inverse output of which is connected to the second input

0 k-ro trigger 12, first exit

N-ro trigger 12 is connected to the second input of the first element And 13, the second output to the second inputs of the second, third and fourth elements

5 AND 14-16, the third input of the second element AND 14 is connected to the direct output of the (H + 1) -th element OR 10, and the inverse. ny output - with the third inputs of the third and fourth elements And 15.

- and 16, the i-th input (H + 1) -th element

ШШ 10 of the first group is connected to the direct output of the i-ro of the element OR 10 of the first group and with the first input of the i-of the And 9 element, the second inputs of the And 9 elements are combined and connected to

 the output of the second element I 14 and to the input of the (N + l) -ro counter 6, the bit outputs of which are connected to the first 3 inputs of the comparison circuit 4, the second inputs of which are connected to the discharge outputs of the register 2 tolerance, and the outputs to the first inputs of cooTse The third and fourth elements are 19 and 20, the outputs of which are the outputs of the device. The device works as follows. The statistical analysis of the characteristics of random numbers reveals the fact that the random numbers under study are known to the law (probability probability distribution functions jt Before the statistical experiment, the abscissas of the specified distribution law are entered into registers I.) The number of probable numbers is entered into the Nth counter 5. The inputs to the device's input 17. The 1st counter 5 (, 2, ..., N) is shifted by multiplying the values of the ordinates of the intended distribution function by the number of number readings (value of the N-ro register 5, Triggers 12 set to the zero state, corresponding to the supply of the resolving potential to the input of the corresponding element And 7, from the output of the Nth trigger, the resolving potential is fed to the input of the element And 13, the counter 6 is set to the state O, the register 2 records the maximum permissible value for the number of statistical experiments of the difference between the theoretical and experimental frequencies of absolute hits. When the first number x arrives at the input 17 of the device, it is compared by the circuits 3 with the registers 1, while in If the contents of the register k-ro (2, ..., N-1) A is longer received at input 17 of the device of Xi (), the output k-th comparison circuit 3 is formed allowing potential. The signal of the end of the reception of the number, podnany to the input 18 of the device, through the open element And 13 enters the elements And 7, while in the bits where the output potential is supplied from the output of the comparison circuit 3, this signal passes through the open elements And 7, OR 11 to subtracting the input of the corresponding counter 5, reducing by one the contents of the counters 94 of those bits where the output potential of the comparison circuit 3 will be the resolving potential. When the second number Xj arrives at the input 17 of the device, processes similar to the above are carried out. Identical processes take place until, when a certain V-ro number x is received, the contents of some counter 5, for example -th, will be equal to zero. Noole. The t-ro code of the counter causes the occurrence of the resolving potential at the inverse output of the t-ro element OR 10, which sets the t-th trigger 12 into one state, the opening th element AND 8 and the closing element AND 7. When entering the information input 17 devices of the next number X; The input signal 18 passes through the AND element 13 to the inputs of the AND elements 7 and 8. Depending on the states of the flip-flops 12 in the bits where the output of the comparison circuit 3 is the resolving potential, this signal enters through the Element And 7 or 8 at subtracting or summing input corresponding to the mentioned circuits 3 comparison of the counters 5. This is how the modulus of the difference between the theoretical value: m and the number of hits in the statistical experiment random numbers in the (Y – 1) interval is calculated. When a specified number of statistical experiments are performed in the Nth counter 5, a zero code is set, therefore, from the inverse output of the element OR 10 N-th discharge, the resolving potential is set by setting N and the trigger 12 to a single state, at which 13 and 14 respectively, prohibiting and resolving potentials are applied. Thus, in each k-th counter there is a difference between the number of hits in the k-th interval of random numbers during the course of a statistical experiment and the number predicted by the distribution law. If the contents of at least one counter 5 is not zero, then from the direct output of the N-ro element OR 10 on, the input potential of the element 14 is fed to the resolving potential. The signals from the input 18 of the device through the element I I4 arrive at the inputs of the elements AND 9 and

counter 6. If the contents of the t-ro counter 5 is slave to zero, then from the direct wave of the t-ro element OR 10 zero potential will be fed to the input of the element AND 9, prohibiting the passage of pulses to the input of the counter 9.

Thus, the input of counter 6 will receive pulses until the contents of all counters 5 are zero, with the result that the contents of count 6 will be equal to the maximum difference between the number of hits in each of the intervals of random numbers during a statistical experiment and the number stipulated by the law of distribution.

If the contents of all counters 5 is zero, then at the direct output of the Nth element OR 10 there will be a potential prohibiting further passage through the AND element 14 of signals from the input 18 of the device, at the inverse output of the N-ro element of the NIII 10 there will be a resolving potential indicating the end of the experiment.

As a result of conducting a statistical experiment, the fact of the truth of the hypothesis about the likelihood of the chosen law of distribution of random numbers is established. If the contents of counter 6 is less than the recorded p register 2 is the maximum allowable for a given number of statistical, 5

absolute frequencies, then at the first output of comparison circuit 4 there will be a resolving potential, which through

0, the And 15 element is fed to the first output of the device 19, otherwise the resolving potential from the second output of the comparison circuit 4 goes through the And 16 element to the second output of the device

5 roystva 20.

This is a statistical analysis of a sequence of random numbers. When analyzing statistical random processes, the values

0 measured value in digital

the code is fed to information input 17, and to input 18 signals are sent to. the points needed to retrieve information.

4 The formation of the integral histogram is carried out by setting the triggers 12 to the state l, (N-l) counters to the state O, and the content of the N th counter must be equal to the number of the intended experiments.

Claims (1)

DEVICE FOR STATISTICAL ANALYSIS OF RANDOM NUMBERS, containing a tolerance register ^ a comparison scheme, subtracting a counter and N analysis channels (N = 1,2, ...), each of which, except for the last, contains a comparison scheme, a register, a counter and the first and second And elements, the output of the first And element in each of the (N-1) analysis channels is connected to the summing input of the counter of its channel, the first inputs of the first and second And elements in each of the (N-1) analysis channels are combined and connected to the output of the comparison circuit channel, the first group of inputs of the comparison circuit in each of the (N-1) analysis channels is connected respectively to the group of outputs of the registers of its channel, and the second groups of inputs of the comparison circuits of all (N-1) analysis channels are combined and form a group of information inputs of the device, the N-th analysis channel contains a counter, about t and moreover, in order to increase accuracy by controlling the parameters of random numbers, additional OR elements, four AND elements, and each of the (N-1) analysis channels are introduced are the third element And, the first and second elements OR and the trigger, and in the N-ii channel analysis a trigger and an OR element are introduced, while the first and second outputs of the trigger in each of the (N-1) analysis channels are connected to the second inputs of the first and second elements AND of their channel, respectively, the third inputs of the first and second elements AND of all (N-1) channels of analysis and the counter of the Nth channel are combined and connected to the output of the first additional element And, the second input · of which is combined with the first input of the second additional element And and connected to the clock input of the device, _{with the} second input of the first additional element And connected with p the first output of the trigger of the N-ro analysis channel, the input of the trigger of the N-ro channel is connected to the output of the OR element of its analysis channel, the inputs of which are connected respectively to the outputs of the counter of its channel, the second output of the trigger of the N-ro analysis channel is connected to the second input of the second and first inputs the third and fourth additional AND elements, the third input of the second additional AND element is connected to the direct output of the additional OR element, the inverse output of which is connected to the second inputs of the third and fourth additional AND elements, the third inputs of which are connected respectively to the first and second outputs of the comparison circuit, the first group of inputs of which is connected respectively to the group of outputs of the tolerance register, and the second group of inputs of the comparison circuit is connected to, the group of outputs of subtracting SU ... 1191919 counter, the input of which is combined with the first inputs of the third elements And (N-1) of the analysis channels and connected to the output of the second additional element And, the second input of the third element And and the direct output of the first OR element in each of (I-1 ) analysis channels are combined and connected to the corresponding input of an additional OR element, the output of the second AND element in each of (N-1) analysis channels is connected to the first input of the second OR element of its channel, the output of which is connected to the subtracting input of the counter of its channel, the output of which is corresponding to the inputs of the second OR element of its channel, the inverse output of which in each of the (N-1) analysis channels is connected to the input of its channel trigger, and the output of the third AND element in each of the (N-1) analysis channels is connected to the second input second element ** ment OR its analysis channel.