SU406199A1 - DEVICE FOR DETERMINING THE SIGN OF THE FUNCTION CHANGE - Google Patents

Description

one

This invention relates to automation and computing.

There are known devices for determining the sign of the EMPLOYMENT / function, which contain a synchro-isato. P connected with a coding block, a block on a block, a block, an older block of analysis, intermediate bits and a low bit, and output circuits "NO and" OR.

The proposed device differs from the known ones in that the bit outputs of the coding unit are connected to the corresponding second inputs of the bit analysis units through the delay unit, and directly to the third corresponding inputs of the bit analysis units, the first outputs of the bit analysis units are connected to the corresponding inputs one output circuit “OR, and the second outputs of the bit analysis blocks are connected to the corresponding inputs of another output circuit“ OR, and the additional output of each previous block is Isa bits associated with the additional input of each successive analysis unit bits, and outputs the first "OR connected to the inputs of the output circuit of output circuits" NO, the output of which is connected to the third zero output device. In addition, the intermediate discharge analysis block contains two input and two additional I, four gate circuits.

“OR and two schemes“ NO, the first inputs of the input circuits “AND are combined. And connected to the first input of the unit, the second and third inputs of which are connected to the second input of the first and second input circuits“ And connected by outputs through the corresponding gate to the inputs the first and second additional AND circuits, which outputs are connected to the corresponding inputs of the first OR circuit and the first NO circuit inputs, the second inputs of which are combined and connected via the second OR circuit to the fourth input of the unit, the first and second outputs to orogo connected to the outputs of the respective circuits' NO, and an additional output coupled to the output unit "of the first OR circuit.

This makes it possible to increase the speed of the device and expand its functionality.

The device contains a synchronizer 1, a coding block 2, a delay block 5, an older bit analysis block 4, an intermediate bit analysis block 5, 6, a lower bit analysis block 7, an output circuit "NO 8 and an output circuit" OR 9, 10. In addition, the intermediate bit analysis block 5 contains two input circuits “And 11, two additional circuits“ And 12, four valves

13, schemes “OR 14, 15 and two schemes“ NO G6.

The output of the coding unit 2 / g-bit binary number is fed to the inputs of the analysis units of bits 4-7 directly and through the delay unit 3, in which it is delayed by one clock cycle. In blocks, 4-7 times of the d / th number are compared with bits (/ -1) of the th number. The positive bit increment signals are sent to you. the device travels through the output circuit "OR 9, and the signals about negative increments of bits through the circuit" OR 10. Both of these circuits are connected to the prohibitory inputs of the output circuit "NO 8, which is connected to synchronizer 1, from which it is input clock signals arrive at the frequency of the numbers being analyzed. In the absence of signals at the outputs of the circuits "OR 9, 10, indicating the equality of the ith and (/ -1) th numbers, a signal appears at the output of the circuit" NO 8.

The operation of all units of the device is synchronized to clock signals, synchronous-isahor signals.

The BLOCKS of the analysis of intermediate bits 5, 6 work as follows (Fig. 2).

Signals "O or" 1 from the output of coding block 2 are sent to the input of one input circuit "AND 11, and signals from" O or "1 are delayed to the input of the other one. One of the gates 13 passes only signals" O and the others valves are only sigals. " At the output of one and additional “And 12” circuits, the signal appears if at its inputs to the left there is “O, and to the right is the signal“ b, indicating a positive bit increment. At the output of another additional circuit "And 12, the signal appears when the signal" 1 is sent to its left input and the signal "O" to the right input, indicating a positive increment and bit. With other combinations of sig nals, at the inputs of additional circuits, “And J2 signals at their outputs do not appear.

The signals from the outputs of the additional circuits "And 12 are fed to the inputs of the circuits" OR 14, 15, included in each block of the analysis of bit 4-5, except for the block of analysis of the younger bit 7. From the output of the circuit "OR 14, the signal goes to the inhibit inputs There are NO 16 bit analysis blocks 7 through the OR circuit 15. With this linking of analysis blocks, bits 4–7, a positive or negative increment signal at the output of a higher bit block serves as a prohibition for outputting increment blocks of lower bits Dov.

Subject invention

Claims (2)

1. A device for determining the sign of a function change, comprising a synchronizer connected to the first inputs of a coding unit, which is connected to a second input to the input of a delay unit, high, intermediate, and low-order analysis blocks and The OUTPUT circuit. "NO, and output" OR, characterized in that, in order to increase its speed and extend functional capabilities, the bit outputs of the coding unit are connected to the corresponding second inputs of the bit analysis units through the delay unit, and to the third the corresponding inputs of the bit analysis blocks are directly, the first outputs of the bit analysis blocks are connected to the corresponding inputs of one output circuit. OR, and the second outputs of the bit analysis blocks are connected to the corresponding inputs of another audio circuit "OR, wherein an additional output of each previous analysis block of bits associated with the additional input of each successive analysis block of bits and the first output circuits outputs" OR connected to the inputs of the output "NO circuit whose output is connected to the third output device. 2. The device according to claim 1, characterized in that the intermediate bit analysis block contains two inputs and two additional circuits "AND, four valves, circuits" OR, and two circuits "NO, the first inputs of the input circuits. And" combined and connected to the first input of the unit, the second and third inputs of which are connected to the second input of the first and second input circuits AND, respectively, connected by outputs through the corresponding gate to the inputs of the first and second additional circuits AND, which outputs are connected to the corresponding inputs of the first OR circuit and lane “NO”, the second inputs of which are combined and connected via the second OR circuit to the fourth input of the block, the first and second outputs of which are connected to the outputs of the corresponding NO circuit, and the additional output of the block is connected to the output of the first OR circuit.