SU1152038A1 - Counting-shifting device - Google Patents

Abstract

ACCOUNT-SLIDING DEVICE, containing two NOT elements and n / 2 counting blocks (and the number of bits of the device), the caldr (which consists of two D-triggers, the AND-OR element and the AND-OR element, and In the block, the C inputs of D-triggers are connected to the output of the AND-OR element, the D input of the second D flip-flop is connected to the direct output of the first D flip-flop, the B-input of which is connected to the output of the I-SHSh-NE element, the inverse output of the second L -trigger connected to the first input of the first group of inputs AND the element I-SHSh-NOT subsequent counting unit, R-input of each D-three yy (vera v1l input device reset, and the first input of the first group of inputs AND I-IPI - clock input device, characterized in that, in order to improve the performance of the device, the second inputs of the first group of inputs AND elements AND-OR-NOT and AND - OR of each counting block is connected to the output of the first element NOT, the input of which and the second inputs of the second group of inputs AND-OR-NOT and AND-OR are the control input of the device, the first input of the first group of AND inputs AND-OR is connected to inverse output of the first B-trigger before In the previous counting block, the output of the I-SHS element of each counting block is connected to the third input of the second group of inputs AND the AND-OR element of the subsequent counting block, the direct output of the second G-trigger of each counting block is And -OR — NOT of this counting unit and with the fourth input of the second group of inputs AND of the AND-OR element of the subsequent counting block, the first input of the first group of inputs AND of the AND-OR-NOT element of the first counting block is connected to the output of the second element NOT, the input of which is the first input second AND input group of AND-OR block of schetchnogo are data input devices.

Description

f11 The invention relates to computing and can be used in automation, telemechanics, sod instrument making. The purpose of the invention is to increase the speed of the device. . FIG. 1 shows a diagram of a shear device; in fig. 2 is a schematic of the converter of the Counter-shear device (FIG. 1) contains the first element NO 1, the second element NO 2, and n / 2 of the counting units 3j. Each j is a countable block (j 1,2,3 ... (1/2) consists of the first) -trigger TT 4j, the second -trigger TT 5j, the element AND-OR-NOT 6 y and the element AND-OR 7 j. The circuit contains reset input 8, clock input 9, control input 1O, information input 11, information output 12. The code converter (FIG. 2) contains a counting trigger T 13, output D is a trigger TT 14, element II-NE 15, the element is NOT 16, the element I-SHSh-NOT 17, the input 18 is the reset of the information input 19, the information output 20, the clock input 21. The counting device operates as follows. To execute the shift operation at the input 8 of the reset, the clock input 9 of the information input 11 of the shearing device is set by signals with a logic level 1, and a signal with a logic level O is connected to the control input 10 of the calculating device O1. The 8 reset signals give the Reset signal. The Reset signal sets the first 3) TT 4 trigger device; and the second J-flip-flop TT 5J in each counting block 3) the resetting device a to the initial state logical O. After receiving the signal Reset the direct outputs of the first D-flip-flop TT 4j and the second B-trigger TT 5j of each counting block 3j an initial signal with a logic level O will be set, and on the inverse outputs of the above-mentioned triggers, an initial signal with a logic level 1. The control signal is fed through the first circuit connecting the counting units 3J of the shear unit, and the input of the first element is NOT 1 and second controlled inputs second groups of inputs AND elements AND-OR-NOT 6j AND AND-OR 7j. In the process of operation of the shearing device, when performing a shearing operation, this control signal prohibits through the I-SHII-NO 6j and AND-OR 7j elements the passage of signals arriving at the first controlled inputs of the second groups of inputs AND-OR-NOT elements 6j and on the first, third and fourth inputs of the second groups of inputs AND elements AND-OR 7). At the same time, the inverted control signal with a logic level 1 from the output of the first element NOT 1 is fed through the second connection circuit of the counting units 3j of the counting device to the second control inputs of the first groups of inputs AND of the AND-OR-HE 6j and AND-7j elements. This control signal from the output of the first element NOT 1 during the operation of the shearing device, when performing a shear operation, allows through the AND-OR-HE 6j and I-ШШ 7 elements) the passage of signals arriving at the first controlled inputs of the first input groups Dov AND elements AND-OR-NOT 6j AND-OR AND-OR 7j. The information signal is fed through the third circuit of the shift register to the input of the second element NO 2 and to the first input of the second group of inputs AND of the I-IPI 7j element of the first counting unit 3j. At the same time, the inverted information signal is fed from the output of the second element NOT 2 to the first controlled input of the first group of inputs AND of the AND-OR-HE 6j element of the first counting unit 3 |. Since the first control input of the first group of Inputs And at the second control input of the second group of inputs AND of the AND-ШШ-НЕ 6j signals with logic levels O are set, then the output of the element AND-OR-NOT 6. forms a signal with logical level 1. This signal from the output of the element AND-OR-NOT 6i passes to the D-input of the first B-trigger TT 4g of the first counting unit 3, preparing this trigger to record single information into it. The single information in the D-flip-flop of the TT is recorded when the trigger signal at the C input of the clock signal changes from a state of Logic 1 to Logic O. The clock signal arrives on the fourth circuit 3 of the commutation system, which connects the first controlled inputs of the first groups inputs AND of the AND-OR of all countable blocks 3j, Since the second control inputs of the second groups of inputs AND of the elements AND-OR 7j are set to a signal with a logical level O, and the second control inputs of the first groups of inputs AND of the elements AND-OR 7 .j set signal with logic level 1, the clock signal changes from the logical 1 state to the logical 0 state, set on the first controlled inputs of the first groups of AND AND 7j elements, will be transmitted to the outputs of the AND-OR elements 7j from which they come to The C-inputs of the first and second D-flip-flops TT 4j and TT 5j simultaneously in each counting block 3. And since only the first D-trigger TT 4 of the first counting block 3 is prepared for recording single information, neither Logical 1 in Logic state On the cue, the information will write down only in this trigger. The direct output of the first H-flip-flop TT 4j with the D-input of the second D-flip-flop TT 5 i provides in each counting block 3 j a sequential rewrite of information from the first to the second 2-flip-flop, and the inverse output link of the second B-trigger TT 5 ji of the counting block 3i.i with the first input of the first group of inputs AND of the AND-OR-HE 6 j and connection of the output of the AND-OR-HE 6 j element with the B input of the first B-tripper TT 4 of the counting block 3 provides a consecutive census information from the second B-flip-flop TT 5. counting unit in the first C-flip-flop TT 4-counting unit 3-. Therefore, when the second clock signal changes from the Logical 1 state to the Logical O state, the single information is written to the second D flip-flop TT 5j of the first counting unit 3j, and when the third clock signal from the Logic 1 state changes to the Logical O state, the single information will be recorded in the first B-three ger TT 4 of the second counting block 3jr Now, if in the time interval between the moments of the clock signal changes from the state of Logic 1 8. 4 in the state of Logic O, set the information input 1 1 of the counter-shear device instead of the information signal with a logic level 1, the information signal with a logic level O, then at the fourth change of the clock signal from the state Logical 1 into the state Logical O in the first and D-trig , the ger TT 4 J. of the first counting block 3 will record zero information, the second D-flip-flop TT Sj of the second counting block 3 will record the single information, and the first D-flip-flop TT 4 of the second counting block 3 and the second) -trigger TT 5j of the first counting Unit 3, the recorded single information is saved. Thus, the described signal arrival process provides for recording and sequential shifting of information in the shift / shift device. To perform a counting operation at the reset input 8, the clock input 9, the information input 11, the control input 10 of the shearing shift device. The signals set with a logic level 1 are set. After that, a reset signal is sent to the reset input 8. The resetting of the triggers of the calculator is done in the same way as for performing a shift operation. The circuits of the information and control signals to the second groups of inputs AND AND-OR-NOT 6 and AND-OR 7-, to the inputs of inverters NOT 1 and NOT 2 and from the outputs of inverters NOT and NOT 2 to the first groups of inputs And elements AND-OR-NOT & and AND-OR 7j are described at the beginning of the work of the shearing device. However, in the process of operation of the shearing device, when performing a counting operation by it, the control signal does not prohibit, but permits through the AND-OR-NOT 6 elements: the passage of signals received at the first controlled inputs of the second groups of AND AND-AND-6 elements :, allows, through the elements AND-OR 7 j, the passage of a set of signals arriving at the first, third and fourth inputs of the second groups of inputs AND elements —OR 7; . In this case, the inverted control signal from the output of the first element NOT 1 does not allow, but prohibits through the elements AND-OR-NK 6 and AND-OR 7. the passage of signals sent to the first controlled inputs of the first groups of inputs AND elements AND-OR -NOT 6j and AND-OR 7j after the B-triggers of the countershift device of each counting unit 3 have been reset to the initial state; at the input of the second G-flip-flop TT 5- formed with a logic level O, and at the B-input of the first D-flip-flop TT A; - signal with logic level 1. A signal with logic level 1 is formed at the D input of the first D flip-flop TT 4, - in the counting unit 3; . passes from the output of the element AND-OR-NOT 6; This counting unit as a result of the fact that at the second control input of the first group of inputs AND at the first control input of the second group of inputs AND AND OR NOT 6 J are set with logic levels O signals Thus, the counting unit 3; prepared to record information in it. Each counting unit 3. The counting unit has four ports, which are determined by the states of the first and second 1) -trigger TT 4, and the TT 5 / of this counting unit, connected in a sequential register. The change in the states of the D-flip-flops of the counting block occurs by signals in the form of changes from Logic 1 to Logic O. This signal is generated at the output of the AND-OR element 7. At a signal with a logic level O at the second input of the first group of inputs I, the signal as a change from Logic 1 state to Logic O state at the third input of the second group of inputs AND and a set of signals with a logic level 1 at the first, second, fourth inputs of the second group of inputs AND elements AND-OR 7; . I The first signal change from co. This is the logical 1 in the state of the logical B-trigger TT 4; and TT 5; respectively, set to state 10, second change, respectively, to state 11, third change, respectively, to state 01 and fourth and 1, respectively, to state 00. The counting process is analogous to those for all triggers of counting blocks 3, J, and between countable in blocks 3;.,. The difference for the first counting unit 3j is that the changing signal at the output of the AND-OR 7j element of this counting unit is formed at a signal with a logic level O at the second input of the first group of inputs And, a signal with a logical level 1 at the second input of the second group of inputs And and the input variable signal from the state of Logic 1 to the state of Logic O. Since the transfer of the calculating device number system to the binary number system is necessary, a transducer can be connected to the device information code 12 code its data input 19 (FIG. 2). When the code obtained after the counting in the shear device is shifted through a code converter at the information output 20, the code bodies are converted into a binary number system. The operation of the code converter is explained by the state table of TT-4 B-flip-flops, | 2I TT 5/2 of the last n / 2 counting block, the shear-counting device and the state of the output .il-trigger of the TT 14 code changer. The table shows the states of the output D-trigger of the TT 14 code converter, obtained in it after

() and (2k + 2) shifts depending on the code determined by the states of the TT 4p D-flip-flops (TT 5 ,, last counting block 3 |, 2 after 2k offsets, where k 1,2,3 .. shift number

To perform a code conversion operation, at input 18 of the reset and clock input 21 of the code converter, signals are set with a logic level.

After that, the reset input of the converter 18 is given a Reset signal. The Reset signal sets the counting trigger T 13 and the D-trigger TT 14 of the code converter to the initial states of Logic O. In this case, if the second D-trigger of the TT, the counting unit 3 is in the Logical O state, then the D input of the B-trigger TT 14 of the code converter receives a signal with a logic level O, and if the second D-trigger of the TT G of the even block is in Logic 1 state, then the D-input of the D-trigger of the TT 14 of the code converter receives a signal with logic level 1. The process of applying a signal another logical level to the D input of the D-trigger TT 14 the code converter is provided with the operation of the elements AND-NOT 15, NOT 16 AND-OR-NOT 17 converter code. These elements analyze the output states of the forward output of the D-trigger TT 14, the direct output of the counting flip-flop T 13 of the code converter, the forward and inverse outputs of the D-flip-flop TT 3 of the counting block 3 (j.

The change in the states of the flip-flops of the code converter is made as a result of the effect on the clock input 21 of the change in the signal from the state Logic 1 to the state Logic.

After supplying (2k + 1) clock signal in the output D-flip-flop TT 14 of the code converter, the information that was recorded in the output D-flip-flop TT 5 "will be set (counting unit 3, after 2h shifts, and the counting trigger T 13 of the code converter will be set to the Logic 1 state. After the (2k + 2) clock signal is applied, the output B-flip-flop TT 14 converts the code converter to either not converted or converted information relative to the one that

was recorded in the output G-flip-flop TT 5.2 of the counting block, the output G-flip-flop of the TT 14 and counting flip-flop T 13 of the code converter after (2k + 1) shifts.

Information after (2k + 2) shifts will not be converted when, after (2k + 1) shifts, the counting trigger T 13 of the code converter is set to Logical 1, the output G-flip-flop TT 14 of the code converter is set to Logical O,

The information after (2k + 2) shifts will be converted when, after (2k + 1) shifts, the counting trigger T 13 and the output D-flip-flop TT 14 of the code converter are set to Logic 1.

If the shearing device contains n / 2 counting blocks, then the maximum number of its states is determined by the ratio N 4 2, and its capacity is determined by the ratio S N - 1, as well as the binary counter with n-discharges.

In the counting mode, each j-th counting unit of the shearing device operates in the synchronous shift mode as a shift register, and the transmission of information signals between the blocks (transfer between blocks) of propagation according to the principle of end-to-end transfer.

The analysis shows that if the speed of the element AND-OR is determined by the time fj, and the speed of the two-bit shift register in the synchronous counting mode T, then the speed of the proposed device will be 1 / nfi, + fj, while in the prototype the speed is determined by the value lf | -nfl (Ci4tj

Thus, the speed of the proposed shear device (when the account) with respect to the speed of the known device is higher in

A ...

ri5.

2 l / yy, -.

In practice, the speed of the T-two-bit shift register in the counting mode is equal to the speed tj of the output D-flip-flop TT. The type of TTL elements of average speed f, 3 200 NS, and the speed TI of the element AND-OR of the same element base, respectively, do not, and at 10, J fj is 3.7.

The proposed organization is the structure of the device due to the new connections

1152038

between the elements, as a result of which a synchronous process of information processing is provided, allowed to increase the speed of the shear device. 3nl2Cyefnffi iu

Faye. 2 5lo /

Claims (1)

COUNTING AND SHIFT DEVICE containing two elements of NOT and n / 2 counting blocks (n is the number of bits of the device), each of which consists of two 0-triggers, an AND-OR-NOT element and an AND-OR element, and in each counting block C-inputs of L-triggers are connected to the output of the AND-OR element, B is the input of the second The D-trigger is connected to the direct output of the first B-trigger, the B-input of which is connected to the output of the element .. AND-IPI-NOT, the inverse output of the second ^ -trigger is connected to the first input of the first group of inputs AND of the AND-OR-NOT element of the subsequent counting block, the R-input of each B-trigger is the input of the device reset, and the first input of the first group of inputs AND of the AND-OR element is the clock input of the device, characterized in that, in order to increase the speed of the device, the second inputs of the first group of inputs AND of the AND elements OR-NOT and AND-OR of each counting unit are connected the output of the first element NOT, the input of which and the second inputs of the second group of inputs AND elements AND-OR-NOT and AND-OR are the control input of the device, the first input of the first group of inputs AND elements AND-OR is connected to the inverse output of the first D-trigger of the previous counting block , the output of the AND-OR element of each counting unit is connected to the third input of the second group of inputs 3 AND of the AND-OR element of the subsequent counting unit, the direct output of the second D-trigger of each counting unit is connected to the first input of the second group of inputs AND of the AND-OR-NOT element count block and with the fourth input of the second group of inputs AND element AND-OR of the subsequent counting unit, the first input of the first group of inputs AND element AND-OR-NOT of the first counting unit is connected to the output of the second element NOT, whose input and the first input of the second group of inputs AND element AND-OR of this counter unit is the information input of the device. 1 1152038