SU1564616A1 - Parallel counter-type adder - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital computers and control systems. The aim of the invention is to extend the functionality by performing the operations of subtracting and inverting operands. Parallel accumulating adder contains in each bit 1 trigger 2, two elements AND 3.4, two elements OR NOT 5.6, element OR 7. Different functions in the adder are performed by applying a set of signals to the inputs 13-16 setting mode . 1 il.

Description

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The invention relates to automation and computing and can be used in digital computers and control systems.

The purpose of the invention is to expand the functionality by performing the operations of subtracting and inverting operands,

j The drawing shows a parallel accumulator adder.

Parallel accumulating adder contains in each bit of 1k

(k

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 1-n) trigger 2, first and second

And 3 and 4 elements, respectively, the first and second elements OR-NOT 5 and 6, respectively, the element OR 7, the inputs

and 9, respectively, of the single and zero potentials of the adder, the outputs

) -10p bits of the adder, information inputs for the, bits of the adder, input 12 reset the adder and the first to fourth inputs 13-16 specify the mode of the adder, respectively.

The adder works as follows.

 Parallel accumulating adder allows you to implement the functions of summation and subtraction of binary operands, the function of the static re

a synchronized binary code receiving function; a synchronized inverse binary code reception function; and an invertor content invert function. The inputs 13, 14 and 15, 16 are supplied with the direct and inverse values of the signals for specifying the type of operation, respectively.

To add binary operands, the preliminary adder is nullified by giving a high signal level to 12 adders.

Consequently, all the triggers of the 2 trap go into the zero state. The permissive signal is applied to the platoons 13 and 16. As a result, the first element AND 3 and the first element OR NOT 5 are prepared to receive information. At the same time, OUTPUT of the first element OR-NOT 5 of the first discharge has a low potential at the OUT, since a high potential from input 8 is constantly supplied to its third input. The bits of the first stage code are passed to the information inputs of the adder. Suppose

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that the first operand is prepared by code 1001 (clause 4). In the first discharge, the unit passes through the first element AND 3 and the element OR 7 and at the counting input of the trigger 2 sets a high potential. The same process occurs in the fourth discharge of the adder. In the adder, T-flip-flops with static-dynamic control are applied, changing their state at the falling edges of the input signals, therefore the states of flip-flops 2 in the first and fourth bits do not change. Thereafter, the first operand 1001 is removed from the inputs 114-111 and, therefore, low potentials are established on them. As a result, low potentials appear at the counting inputs of flip-flops 2 of the first and fourth bits, therefore, they go into one state. A low potential from the inverse output of the trigger 2 of the first bit is applied to the third input of the first element OR NOT 5 of the second bit and at the counting input of the second trigger 2 sets a high potential. A high potential is also established at the counting input of the trigger 2 of the second bit. After that, the adder is ready to receive the second operand.

The second operand is also provided to the information inputs. Suppose that the second operand is represented by code 0111. At the same time, high potentials appear at the counting inputs of flip-flops 2 of the first and third bits, since the input logic units pass through the first elements And 3 of the corresponding bits. In the second discharge, the unit from the information input 11g is fed to the first input of the first element OR NOT 5 and at its output sets a low potential. Therefore, the trigger 2 of the second bit goes into a single state. A low potential from the inverse output of trigger 2 of the second discharge closes the first element AND 3 of the third discharge and converts the corresponding trigger 2 to the unit state. Thus, in the triggers 2, the code 1111 is recorded. After that, the second operand is removed from the information inputs 114-114. High potentials are set at the counting inputs of flip-flops 2 of the second, third, and fourth bits, and a low potential is set at the counting inputs of flip-flop 2 of the first bit. As a result, the trigger 2 of the first discharge goes to the zero state, the high potential from the inverse output of which establishes a low potential at the output of the first element OR-NOT 5 and at the counting input of the trigger 2 of the second discharge. Trigger 2 of the second bit goes to the zero state, in turn, triggers Trigger 2 of the third bit to the zero state, and so on. As a result, a code 0000 is written in all four bits of the adder (with the fifth digit of the adder becoming unit state). To subtract the binary operands, the spreading signal is fed to inputs 14 and 15. As a result, the second element, AND 4 and OR-HE 6, are prepared to receive information. At the same time, at the output of the second element I 4 of the first bit, there is a low potential, since a low potential from the input 9 is constantly supplied to its third input. Suppose that a decrementing one, which is a code 10,000, is preliminarily entered into the bits of the adder. served on information inputs 11p-114 adder. Suppose that the deductible is represented by code 0111. In the first discharge, the unit at the first input of the second element OR- NOT 6 sets at its output a low potential, which through the element OR 7 at the counting input of the trigger 2 of this discharge forms the trailing edge of the control signal translates it into a single state. The same process occurs in the second and third bits of the adder. The high potential from the direct output of trigger 2 of the first discharge opens the second element AND 4 of the second discharge and sets a high potential at the input of the corresponding trigger 2. The same process occurs in the third discharge of the adder. The high potential from the direct output of the trigger 2 of the third bit sets the output of the second element OR-KE 6 to even; of the true bit, the zero potential, which through the OR element 7 is fed to the counting input of the trigger 2. In the trigger 2 of the fourth bit, the unit state is set.

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Thereafter, operand 0111 is removed from the information inputs. Low potentials are set at the counting inputs of flip-flops 2 of the second and third bits. As a result, the triggers 2 of the second and third bits go into the zero state

The function of a static register with v synchronized reception of a binary code is carried out as follows.

The pre-adder is zeroed by applying a signal to input 12. Opera 5 Rand is fed to the information inputs 11p-11 ,,. A clock signal is provided via an input 13 of an adder.

The function of the static register of synchronized inverse reception of a binary code is carried out as follows.

The pre-adder was nullified by applying a signal to input 12. PoshGe. of this, inputs 13 and 14 are simultaneously supplied with a clock signal. At the outputs of the second OR-NOT elements of the 6 bits of the adder, high potentials are established, which through the elements of OR 7 are supplied to the counting inputs of the corresponding triggers of the 2 bits of the adder. After that, the clock signal is removed from the inputs 13 and 14 of the adder. At the outputs of the second OR-NOT elements of the 6 bits of the adder, low potentials are set, which, through the OR 7 elements, on the counting inputs of the triggers of the 2 bits of the adder, form the trailing edges of the control signals, which bring them to the Q state. Accepted operand is fed to the information inputs 11p-11, and the receive clock is input to 14, In triggers 2, the inversion of the binary operand is set.

The function of inverting the contents of the adder is carried out as follows.

The sync signal is fed to inputs 13 and 14. At the outputs of the first elements OR-NOT 5 or the second elements OR-NOT 6, which depends on the contents of the previous discharge, high potentials are set, which through the elements OR 7 are applied to countable ones. The inputs of the trigger 2 bits of the adder. After this, the sync signal is removed from inputs 13 to 14 "On the counting inputs of the flip-flops 2 digits of the adder, the rising edges of the control are formed

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signals. In triggers of 2 bits of adders, the content code in- jersey is set up;

Parallel accumulating sumforr containing in kM bit (k f ... n, n is the digit number) tripletfep, the first and second elements are AND, nep is the OR-NOT element and the element is OR, 1 | features the reset input of the adder connect with; the installation inputs in O of the trigger bits of the adder, the direct outputs of which are the outputs of the corresponding digits of the adder, the outputs of the first and second elements AND the k-ro bit of the adder are connected to the corresponding inputs of the OR element of the k-ro bit of the adder, information - the fifth input of the k-ro bit of the adder is connected with the first inputs of the first and second elements AND of the k-ro bit of the adder; the inverse output of the trigger of the k-ro bit of the adder is connected to the second input of the first element of And (k + 1) -ro raz da adder, about t l and: a y i and so that, with the aim of expanding audio functionality by performing operations You are a power inversion and operands, it co 4erzhit a k-th second discharge element

OR-NOT, and the outputs of the first and second elements of the OR-NOT k-ro bit of the adder are connected respectively to the third and fourth inputs of the element OR k-ro bit of the adder, the output of which is connected to the counting input of the k-ro trigger of the adder, information the k-ro input of the adder is connected to the first inputs of the first and second elements OR the k-ro discharge of the adder, the first to the fourth inputs of the adder mode setting are connected to the third inputs of the first And elements and the second inputs of the second And elements, elements or not and wto elements of the OR-NOT bits of the adder, respectively, the second input of the first element AND the k-ro bit of the adder is connected to the third input of the first element OR the k-ro bit of the adder, direct output of the k-ro trigger the adder is connected to the third inputs of the second elements AND and OR-NOT (k + 1) -ro bits of the adder, the inputs of the unit and zero potentials of the adder are connected respectively to the second input of the first element AND and to the combined third inputs of the second elements AND and OR-NOT the first raz yes adder.

Claims (1)

Claim A parallel accumulating adder containing in the kth digit (k = '... η, η is the bit capacity of the number) trigger, first and second elements AND, nep-jg 1 ^ th element OR NOT element OR, 1) [the input of the adder reset is connected to the inputs of the setting to ”0 triggers of the adder discharges, the direct outputs of which are outputs of the corresponding 5 discharges of the adder, the outputs of the first and second elements of the nth discharge of the adder are connected to the corresponding inputs of the element OR to of the adder discharge, the information input of the 20th adder discharge is connected to the first inputs of the first and second elements of the And-adder discharge, the inverse trigger output of the ad-d discharge of the adder is connected to the 25th second input of the first And element (k + 1) th category adder, characterized in that, in order to expand functionality by performing operations of raising and inverting operands, it contains the second element in the OR NOT, and the outputs of the first and second elements OR NOT of the adder category are connected to the third and fourth inputs of the OR element of the ad category, respectively, the output of which is connected to the counting input of the trigger of the ad category, the information input is th bit of the adder connected to the first inputs of first and second OR-NO element of the kth adder discharge, the first to fourth adder mode reference inputs are connected to third inputs _hours first element and with the second inputs of second aND gates, the first OR-NO elements and second elements OR NOT discharges of the adder, respectively, the second input of the first element AND of the k-th adder is connected to the third input of the first element OR to the k-th adder, the direct output of the trigger of the k-th adder is connected to the third inputs of the second AND and OR -NOT (k + 1) -to the discharge category of the adder, the inputs of the unit and zero potentials of the adder are connected respectively to the second input of the first element AND and to the combined third inputs of the second elements AND and OR NOT the first discharge of the adder.