SU907793A1 - Digital frequency discriminator - Google Patents

Description

one

The invention relates to a pulse technique, in particular, to devices for determining the magnitude and sign of the frequency difference between independent time pulse sequences, and can be used in frequency information processing systems and automatic frequency control systems.

Known digital frequency discriminator containing element and triggers and CQ

However, this device does not allow processing of frequencies of more than two pulse sequences simultaneously.

The closest in technical essence to the invention is a digital frequency discriminator comprising a clock pulse generator, two synchronization blocks and three flip-flops 12.

This zirp frequency discriminator does not allow discriminating more than two pulse sequences at the same time, while it is often necessary to compare the difference and sign of two frequencies with the third frequency, for example, when shaping frequencies that vary relative to the reference frequency in a given range. In such cases, it is necessary to use two serially connected discriminators, which considerably complicates the device, impairs its speed and reliable operation.

The purpose of the invention is to expand the functionality by increasing the number of simultaneously discriminated frequencies of pulsed sequences.

This goal is achieved by the fact that a digital frequency discriminator containing a clock generator, two synchronization blocks and three flip-flops, the clock pulse output connected to the trigger inputs and clock inputs of the synchronization blocks, the information inputs of which are connected to the input terminals of the device, the direct output of the first synchronization block is connected to the first E-inputs of the first and second flip-flops, the second 3-inputs of which are interconnected, and the third 3-input of the second flip-flop is connected to n My output is the first three Hera, the inverse output of which is connected to the first G7-INPUT of the third trigger, the second 5-input of which is connected to the first K-input of the first "trigger, the second K-input of which is connected to the third 3-input of the third trigger and inverse the output of the first synchronization block, additionally entered are the serially connected input bus, the synchronization block, the NAND element and the NOT element whose output is connected to the first K input, and the input to the second D input of the first trigger, and the clock input of the auxiliary sync block This unit is connected to the information input of the second synchronization unit, the direct output of which is connected to the second input of the NAND element. FIG. I shows the block diagram of the digital frequency discriminator in FIG. 2 - temporary tsaagrams, according to the lower work of the proposed discriminator. The device contains input buses e 2 and 3, a generator of 4 clock pulses, the main 5 and 6 and an additional 7 blocks of synchronization, element 8 AND-NOT, element 9 NOT and triggers 10, Pi 12. The device works the following way. The pulses of the first sequence f from bus 1 are fed to the information input of the synchronization unit 5. The pulses f from the generator of 4 clock pulses are fed to the clock input of this block. At the outputs of the synchronization unit 5, pulses are formed, the duration of which is equal to the period of the clock pulses, and the frequency of the signal frequency t "The pulses from the direct output have unit levels, and from the inverse - zero. Fig. 2 shows pulses removed from the direct output of block 5 and tied to the falling edge of the corresponding pulses f (,, Pulses f. Are delayed relative to the falling edge of the clock pulses for a time determined by the elements of block 5 and go up to the first O- the trigger inputs 10 and II, and the f pulses from the inverse output of block 5 are fed to the second K input and the third 3 input, respectively, of triggers 10 and 12. The pulses from the second sequence fj, from bus 2 are fed to the information input of block 6, to the clock input of which impulses f are applied. Lok 6, pulses f are formed, the duration of which is also equal to the clock pulse period, and the frequency is the frequency of the signal fjj. The pulses fa lead over the trailing edge of the corresponding ff pulses and are fed to the first input of element 8 AND –NE. The pulses of the second sequence 2. are also fed to the clock input of block 7, to the information input of which pulses of the third sequence f from bus 3 are supplied. Block 7 is identical to blocks 5 and 6. Zero-level pulses fi are output from the inverse output of this block, the duration of which is; equal to the period of the signal%, and the frequency - the frequency of the signal fn. The pulses f (FIG. 2) are formed on the falling edge of the pulses tj and fed to the second input of the element 8 AND-NOT, which outputs the zero signal when its inputs ui are fed to the unit level signals, therefore each zero level pulse f prohibits the passage to the output element 8 of a single pulse of a single level sequence fL. Zero-level pulses fp are output from the output of element 8 of the IS-NOT, the duration of which is equal to the signal period ff -, and frequency to the difference frequency of the pulse sequences f f. (Delays introduced by the device elements, in Fig. 2 are not shown conventionally to simplify the principle its operation. Pulses fp are supplied to 3 inputs of the trigger 10 and 11 and to the input of element 9. NOT. From the output of element 9, there are no pulses of a single level FR, which are fed to one of the K-inputs of trigger 10 and to one of the -gings of trigger 12. Pulses fp delayed. 59 relatively rear about the front of the corresponding clock pulses at the time determined by blocks 6 and 7 of the elements 8 and 9. At the inputs of the flip-flops 11 and 12 coinciding and alternating pulses of sequences and tp are excluded. At the C-points of the flip-flops are 10, 1 G and the clock pulses are given. fj and fp ie change the state of trigger 10, because they go in antiphase on both the jj inputs and the K inputs of the trigger 10 simultaneously. Alternating pulses. f- and fp alternately change the state of the trigger 10 on the falling edge of the respective clock pulses, and if the pulse f arrives, then the trigger 10 is set to one state, and the next pulse fp moves it to the zero state. Thus, the trigger 10 remembers such a pulse, which of the sequences r and fp was the last. If there are a series of two or more pulses f in the absence of pulses fp, the first of the pulses f sets toygegeo 10 to a single state, as a result of which subsequent pulses of a single level fj arriving at one of the 3 inputs of the trigger 11 can control the single state last one. At the same time, after the arrival of the pulse f at the I input of the trigger I1, oi turns into a single state at the falling edge of the first pulse entering its C input at the presence of the pulse f, and returns to the zero state at the falling edge of the second clock pulse . As a result, pulses are formed at the output of trigger I1, the duration of which is equal to the period of clock pulses.

Trigger 12 works in the same way when there is an additional two or more fp pulses in the absence of pulses.

Thus, at the output of the trigger 1 I, pulses Af are emitted. at f., and at the output of the trigger 12 pulses Af at f -f2f3 “FIG. 2 shows the case when, the frequency of the output pulses of trigger II and 12: is equal to uf. f;, - (f2-f3).

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fo-f IMnprf equality of frequencies fjj and

11 and 12

trigger output pulses

are missing.

The synchronization unit is a signal fjj. A fourth pulse sequence ff is applied to the information input of this block, - Then a differential frequency pulse sequence will be input from the device output

uf (f -f5) - ().

The use of the invention will expand the functionality of the digital frequency discriminator Minator and the simplest means to ensure the processing of three or more frequencies, which in turn leads to an increase in the reliability and speed of the device.

Claims (2)

Invention Formula A digital frequency discriminator containing a clock pulse generator, two synchronization blocks and three flip-flops, the clock generator output being connected to the trigger inputs C and the clock inputs of the synchronization blocks whose information inputs were connected to the input buses of the device, while the direct output of the first synchronization block connected to the first iD-inputs of the first and second trig | Gerov, the second P-inputs of which are connected3 It should be noted that for the synchronization blocks to work correctly, the frequency of the pulses cos supplied to the their clock, vkody was greater than the pulse frequency applied to the inputs informatsnonnye. Fishpulse followers f 3 are independent in the manner of menia. Obviously, the synchronization unit 7, the CID element 8 are NOT, the element 9 can NOT be turned on and so that the clock signal for the synchronization unit 7 is used. signal. In this case, the frequency of the output pulses of the device is equal to Af (the pulses Af are output at f. Pulses uf-. At f ° by using the second additional synchronization unit and additional elements NAND and NOT and switching them on accordingly, can be simultaneously used as a clock signal for synchronization unit 7, the signal f, and for the second one, are complemented with each other, and the third 9-input of the second flip-flop is connected to the forward output of the first flip-flop, the inverse output of which is connected to the first 3-input of the third flip-flop of the second To the first K-input of the first trigger, the second K-input of which is connected to the third D input of the third trigger and the inverse output of the first synchronization unit, characterized in that in order to expand its functionality, the sequentially connected input bus is additionally introduced into it NAND and CB element whose output is podkoshchochen to the first K-input and input to the second JJ-input of the first trigger with the clock input of the additional unit synchronous A1, connected to the information input of the second synchronization unit Direct Access is connected to the second input of the element ii-he. Sources of information received during the examination 1 USSR author's certificate 9 621066 K.1. H 03 D 13/00 1978. 2. Patent POWER B 373532A cl. G973. and g Ca "9% s aSs 1 CJ; ikc) "S Wi - (I S S e " m h ua 45 4j g . h “;