SU1378076A1 - Data transceiver - Google Patents

Abstract

This invention relates to the accumulation of information. The purpose of the invention is to increase the speed of information exchange. In the central unit 1. The counter 5 generates a control signal when recording interband gaps. When interrogating the peripheral blocks, the 4 clock signal through the element 15 and the key element 6 is transmitted to the two-wire line 2. When the counter 5 is filled, the recording unit 3 is switched to the interband gap filling mode. The counting of clocks from the two-wire line 2 is performed by the addressing unit 11 via the receiving element 9 and the shift register 7 is shifted. The addressing unit 11 generates a signal for enabling the operation of the key element 8 through the element 16 and the element 17 of the delay. The selector 10 pulses for duration select interband gaps, which correspond to

Description

WITH

00

O5

A longer high-level signal on the two-wire line 2 is used. When recording inter-band gaps, such a period is 3 / DT, where T is a clock period, and three recording pulses are formed through 1 / 4Т, 3 / 8Т and 2 / 4t from the beginning of the clock period. 3 il.

t

The invention relates to the accumulation of information, namely, devices for receiving and transmitting information.

The aim of the invention is to increase the speed of information exchange.

Figs. 1 and 2 show functional diagrams of a device for receiving and transmitting information; Fig. 3 shows timing diagrams of the operation of the proposed device.

A device for receiving and transmitting information contains a central unit 15 connected by an output via a two-wire line 2 to an input of a recording unit 3 and with peripheral blocks 4, the control output of the central unit 1 connected to the control input of a recording unitJ The central unit 1 contains a serially connected counter 5 pulses, the output of which is the control output of zeitral 1 of block 1, and the key element bd whose output is the output of central block 1,

 from the peripheral blocks 4 contains the shift register 7, the inputs of which are the information inputs of the peripheral block 4 connected to the inputs of the key element 8 connected by the output to the two-wire line 2 and to the input of the receiving element 9 connected through the selector 10 pulses in duration to the setting one the input of the addressing unit 11 and directly to the synchronization inputs of the shift register 7 and the addressing unit 11 connected by the first input to the control input of the shift register 7.

Recording unit 3 comprises a pulse generator 12, a receiving element 13, whose input is an input of a recording unit 3, and a multiplexer 14 connected by a first input to a control input of a recording unit 3 and a second input to an output of receiving element 13.

In addition, the Central unit 1 contains the element And 15, each peripheral unit 4 contains a series-connected element And 16 and the element

5 17 delays, and the recording unit 3 contains a series-connected counting trigger 18 and a driver of 19 bipolar pulses, a pulse counter 20, an HE element 21 and an And 22 element,

O connected by the inputs to one output of the pulse counter 20 and fpeTbeMy and the fourth input of the multiplexer 14 connected by the output to the input of the counting trigger 18 by the fifth input through

 the element NOT 21 to the control input of the recording unit 3 and to the corresponding input of the receiving element 13, the sixth input to the unit voltage level and the sixth and seventh inputs to

0 the remaining inputs of the counter 20 pulses, charged by a synchronizing input to the output of the generator 12 pulses and a control input to the control input of recording unit 3, and in the central unit 1 And 15 element is connected between the output of counter 5, pulses and key element 6 and connected by one of the inputs to the input of the counter 5 pulses and to the control

 the input of the central unit 1 connected to the control output of the recording unit 3, which is the output of the AND element 22 of the recording unit 3, and in each peripheral unit 4 an AND 16 element

5 is connected by an output through a delay element 17 to the input of a key element 8, by a first input to an output of a receiving element 9, by a second input to a second output of addressing block 11 and a third input to an output of shift register 7.

The device works as follows (Fig.1 and 3).

By clock signals A, corresponding to

5 stvz skinny one bit of the recorded information in the central unit 1,

five

generate synchronization signals B to two-wire line 2 (zero level signals). The information is transmitted to the two-wire line 2 from the peripheral units 4 in turn. During the period of interband gaps (I) on the two-wire line 2, the clock signal is not issued from the central unit 1. During this period, the peripheral units 4 are reset (they embed the addressing unit 11 and enter information into the shift register 7).

The operation of the central unit 1: with a pulse counter 5, the shaping of 5 pulses is carried out;

control signal when recording interband intervals (P). When interrogating the peripheral blocks, the 4 clock signal is transmitted via the AND 15 element and the key element 6 to the two-wire line 2 (a low level signal with a duration of 1 / 4-1 / 3T).

When the counter of 5 pulses is filled (in the gap) with the signal B, the element 15 is locked, and the recording unit 3 is switched to the mode of filling the inter-band spans (P).

The operation of the peripheral unit 4: the clock counting from the two-wire line 2 is carried out, by the addressing unit 11 through the receiving element 9, the same shift of the shift register 7 is performed with the same signal. The addressing unit 11 generates a signal for enabling the operation of the key element 8 through the element 16 and the element 17 of the delay. In the presence of O at the output of the register 7 shift element And 16 is locked and the key element 8 is disabled. If there is 1 key in the shift register 7 shift, element 8 is connected via delay element 17 and element 16, if there is a resolution signal from addressing unit 11 on two-wire line 2, the signal is kept low. The duration of the key element 8 is set by the delay element 17 (3 / 4-4/5 clock period T), i.e. change the duty cycle of the signal B. The selector of 10 pulses for the duration selects interband gaps, which correspond to a longer high-level signal (more than T) on the two-wire line, and zero the unit

11 addresses

The operation of block 3 of the record (Fig.2 and 3) clock frequency set by the generator

12 pulses, and the coding of the information signal for recording (between

the exact pulses E) are formed using a pulse counter 20 and a multiplexer 14. Depending on the information signal received from the two-wire line 2 through the receiving element 13, the operation mode of the multiplexer 14 is set. And the matching element 22 creates a clock signal A for the central unit 1. When zapistg intermonth intervals by signal B change the division ratio of the counter 20 pulses .. On the magnetic head (not shown) by the former 19 bipo

five

0

five

0

five

0

sy G alternating polarity on the fronts of the signal Ж, coming from the counting trigger 18.

When writing O, two pulses are formed (Fig. 3g), the needle is spaced from the beginning of the clock period at intervals equal to 1/4 and 3/4 T (where T is the clock period). When recording 1, three pulses are formed at intervals of 1/4, 2/4 and 3/4 T from the beginning of the clock period. When recording interband gaps, the clock period is equal to 3/4 T, and three recording pulses are formed at intervals of 1/4, 3/8, and 2/4 T from the beginning of the clock period.

Interrogation of the peripheral units 4 is carried out in one word. The words are separated by interzone gaps.

Claims (1)

Invention Formula A device for receiving and transmitting information containing a central unit connected by an output via a two-wire line to an input of a recording unit and peripheral units, the controlling output of the central unit connected to the control input of a recording unit, the central unit containing successively connected The 1GM pulses counter, the output of which is the control output of the central unit, and the key element, whose output is the output of the central unit, each of the peripheral units contains a shift register, inputs to orogo are infO15matsionngmi inputs ne riferiynogo block podklyuchennpt output to the input key element connected to the output of the two-wire line and to the input of the receiving element connected across the output pulse duration selector entry to the mounting block and addressing directly to sinhronizirugogattm the inputs of the shift register and the addressing unit connected by the first output to the control of the single input of the shift register, and the recording unit contains a pulse generator, a receiving element whose input is the input of the recording unit and a multiplexer connected by the first input to the control input of the recording unit and the second input - to exit at element, for example, so that, in order to increase the speed of information exchange, an AND element is inserted into the central block, And consecutively connected And and a delay element are inserted into each peripheral block, and a sequential connected trigger is entered into the recording block and a bipolar pulse former, a pulse counter, a NOT element, and an AND element connected by inputs to one output of a pulse counter and the third and fourth inputs of a multiplexer connected by an output to the input of a counting trigger, the fifth input Erez element is not to pack 2 the equal input of the recording unit and the corresponding input of the receiving element, the sixth input to the unit voltage level and the sixth and seventh inputs to the remaining outputs of the pulse counter connected by the synchronization input to the output of the pulse generator and the control input to the control input of the recording unit In the central unit, the element I is connected between the output of the pulse counter and the input of the key element and is connected by one of the inputs to the input of the pulse counter and to the control input of the central unit connected to the control output of the recording unit, which is the code of the AND element of the recording unit; in each of the peripheral blocks, the AND element is connected via the delay element to the input of the key element, the first input to the output of the receiving element, and the second input to the second output of the addressing block and the third input is to the output of the shift register. FIG. 3