SU608161A1 - Information processing arrangement - Google Patents

Description

one

The invention relates to computing, in particular, to specialized information processing devices.

The information ordering systems are known that are executed both on the basis of universal computers and on the basis of digitalized devices 1. The ordering systems on the basis of universal digital computers use special ordering programs containing a whole series of service operations (selection of commands, formation of intermediate addresses, checking conditions of exit from the cycle, etc.), resulting in a large expenditure of computer time.

The closest in technical essence to the proposed is an information sorting system comprising a memory block, the first and second clock outputs and information input and output of which are connected respectively to the first and second clock signals and the first information output and switch input, the array separation unit, the first the input of which is connected to the second information output of the switch, the control unit, the first input-output of which is connected to the control input-output of the array separation unit, and the second The control output of the control unit is connected to the control input of the switch (2.

A disadvantage of the known system for sorting information is its low speed.

The purpose of the invention is to increase speed.

This is achieved by the fact that the system contains the first and second comparators, the first and the second buffer storage blocks, the OR element, and the first and second clock outputs of the switch are connected to the corresponding inputs of the first and second comparators, the control inputs-outputs of which are connected respectively to the third and the fourth inputs / outputs of the control unit; the output of the first comparator is connected to the second input of the array separation unit, the information output of which is connected to the information inputs of the first and second signals of the core storage blocks, the first and second inputs of the sync signals of which are connected to the corresponding outputs of the sync signals of the array splitter and the second comparator, respectively, the outputs of the extreme states of the first and second buffer storage blocks are connected to the corresponding inputs of the control unit, and their information outputs via the OR element with information input of the switch.

The drawing shows the structural scheme of the system.

It contains a memory block 1 consisting of two storage devices (memories) 2 and 3. The outputs of the clock signals 4 and 5, as well as the information input 6 and the output 7 of the memory block 1 are connected respectively to the first and second inputs of the clock signals and the first information output and the input of the switch 8. The second information output of the switch 8 is connected to the first input of the array separation unit 9, the control input-output of which is connected to the first input-output of the control unit 10. The second output of the control unit 10 is connected to the control input 8 of the switch. The first and second outputs of the clock signals of the switch 8 are connected to the corresponding inputs of the first 11 and second 12 address comparators, the control inputs-outputs of which are connected respectively to the third and fourth inputs-outputs of the control unit 10. The output of the first comparator 11 is connected to the second input of the array division 9 The information output of which is connected to the information inputs of the first 13 and second 14 buffer storage blocks (BZB), the first and second inputs of the sync signals of which are connected to the corresponding output m of the sync signals, respectively, of the array separation unit 9 and the second comparator 12. The BZB 13 and 14 extreme conditions outputs are connected to the corresponding inputs of the Control unit U, and their information outputs through the OR 15 element - to the second information input of the switch 8.

The proposed system implements a procedure of random ordering of information, starting with the analysis of the younger bits of the feature used for ordering, in order of decreasing or increasing. Consider the operation of a system in which the memory block 1 consists of two chargers 2 and 3 with sequential presentation of information that have a separate track with recorded sync pulses (magnetic drums or stationary magnetic dIsks). It is assumed that all the words of the ordered array of information have the same number of bits n, of which the m first bits are occupied by the feature code, and the (n-m) bits are the information word itself.

Let us consider the system operation by the example of array ordering in order of decreasing the code of the attribute of its words.

In the initial state, the memory 2 is perpetual, and the memory 3 is receiving, and a disordered array of information is located in memory 2. On command from control unit 10, switch 8 communicates points A and A, B and B, C and B G and G Memory 2 is turned on for reading, and Memory 3 is for writing information. From control unit 10, the code of the starting address of the disordered array of information located in the memory 2, as well as the code of its volume, is entered into the first address comparator 11. B.LOCK 10 control adjusts the block 9 for dividing the array to analyze the lower bit of the array word.

After these preparations, an initial scan of the array begins. When the disk 2 is rotated, the sync pulses from the clock 4 output of memory 1 through the switch 8 are fed to the input of the first address comparator I. At the moment of comparing the code of the current address of the disk 2 to the code of the initial address of the array being written to the comparator 11, the outputs begin to flow to the input of the array separation unit 9. At the same time, from the information output 7 of memory 1, through the switch 8, the information itself enters the input of the array separation unit 9. The information is provided by a serial code P. rd d r after discharge and clocked by clock pulses. With the passage of each word of the array through the separation unit 9 in a certain tact, an analysis of the code of the youngest bit of its sign is performed. If the code of the next word in the array contains the code “b”, then the array separation unit 9 generates a pulse and sends it to control unit 0, which counts these pulses. The actual information from the splitter E unit is not transmitted anywhere during the initial scan of the array. After the entire array of information has been reviewed by the separation unit 9, in the control unit 10 of the byte control, the number of array words containing the code "1 in the lower category of the feature" is counted.

After the initial scan of the array, preparations are made for the first stage of ordering. To do this, from the control unit 10, the code of the starting address of the disordered array of information located in the memory 2 and the code of its volume are again entered into the address comparator 11. In the second address comparator 52 of the control unit 10, the codes of the first and second initial addresses on the disk 3 are entered, beginning with which the words of the ordered array will be recorded in the memory 3, containing respectively 1 and O in the lower sign category. At the same time, the code of the second starting address is calculated as the sum of the code of the first starting address and the code of the number of words in the array, containing the "1 in the lower digit of the sign obtained as a result of the initial scan of the array. Block 0 control: Lenin configures block 9 of dividing the array for the analysis of the youngest and following 10 second sign bits. BZB 13 and 14 are zeroed (cleaned).

Next, the first stage of ordering begins - at the youngest level of the feature. As in the initial scan of the array, at the time of comparing the code of the current address of the memory 2 with the code of the initial address recorded in the comparator II, information separation and synchronization signals are sent to block 9. The separation unit, as in the initial

review, carries out the analysis of the lower bit of the characteristic of each word. The words passed through block 9 of separation will be sent to the information inputs of the first and second BZB, respectively 13 and 14. At the same time, if in the low order of the sign of this word contains "1, the block 9 of the split sends the sync signals to the first input of the sync signals of the first BZB 13, and if, in the lower order, the sign of the given word contains "A. then block 9 provides the sync signals to the first clock input of the second BZB 14. Thus, when passing through the separation block 9, the ordered array of information will be divided into two subarrays of words, namely the subarray of words containing "1, and the subarray of words containing" O , in the younger category of the sign. These subarrays will be recorded respectively in the first 13. And the second 14 DLB. Blocks 13 and 14 may have insufficient capacity and therefore may overflow with information during operation. In a joke of overflow at least one of the blocks 13 or 14, they send overflow signals to the control block 10 from the outputs of extreme states.

The control unit 10 in this case delivers the corresponding signal to the comparator 11 and it stops feeding the clock signals (and hence the information) to the supervision unit 9. In this case, in the comparator 11, the address of the disk memory 2 is stored, at which the information supply was interrupted in the separation unit 9. This address, when resuming circulation to memory 2 on the next turn, will serve as the “updated starting address of the array to be arranged.

When the disk 3 is rotated, its sync signals from the output 5 of the memory unit through the switch 8 will be fed to the input of the second address comparator 12. At the moment of comparing the code of the current address of the memory 3 with the code of the first starting address recorded in the comparator .12, from its output to the second the sync input of the first BZB 13 will begin to receive the sync signals. The information in block 13 will be read from it by a sequential code through the OR element. 15 and the switch 8 arrive at the information input 6 of the memory 1 and write to the desired address in the disk 3. If all the information is read from block 13 and recorded in memory 3, the block 13 from its output of extreme conditions will give the corresponding signal to the block 10 controls The control unit 10, in turn, will send a signal to the comparator 12 and the latter will stop sending the clock signals to the HUZ 13. At the moment of comparing the code of the current address of the charger 3 with the code of the second starting address recorded in the comparator 12, the clock signals will start coming from its output during the clock, the clock signal input of BZB 14. Information from block 14 will be read through the element OR 15 and switch 8 will be fed to input 6 of memory block 1 and written to memory 3 at the desired address. If all information will be read from block 4 and recorded in memory 3,

block 14 from its output chxtrem.x. () (. the transmitter will send a signal to control unit 10, which, in turn, will send a signal to the co-op. 12, and the latter will stop sending clock signals to block 14. At the moments of stopping the sync signals to the second inputs of the sync signals of the first and second BZB 13 and 14 in the comparator 12 memorize the corresponding addresses at which the recording of information in the memory 3 was interrupted. These adros will be the first and second updated addresses of the comparator 12, respectively, when they are written in memory 3 following .e pieces of information. Esyi both BZB 13 and 14 are not overflowed, on the next turn of the transmitting memory 2, the current address will be compared. The memory 2 with the updated initial address of the comparator 11, and the procedure of the system will be repeated. analyzes the next, second bit of the sign of the word passing through it, and sends a pulse to the control unit 10 each time when the word contains in the second bit of the phrase "I. The first stage of array ordering will end when all array words are passed through block 9 of array partitioning and recorded in memory 3 {the volume counter of the array being sent in comparator 11 is reset). As a result of this stage, the array of information will be partially ordered, i.e., ordered by the younger digit of the feature. The entire partially ordered array of information will be compactly located in memory 3, i.e., both subsets of its words containing, respectively, “1 and” 0 in the younger sign category, will be located one after the other without empty areas between them. This was achieved by thanking the computation of the second starting address written into comparator 12, based on the result of counting the number of array words containing "in the lower sign of the feature, during the initial scan of the array.

The second stage of ordering is the second time between the sign. The above ordering procedure should be Applied to the already partially ordered as a result of the previous stage. PA array located in the memory 3. At the second stage, the arrangement of the memory 3 should be transmitting, and the memory 2 - receiving. Therefore, on command from control unit 10, switch 8 communicates the points A with G, D and A, B with C, C with B. The memory 3 switches to reading, and the memory 2 to z; a. Next, the control unit 10 enters into the comparator II the code of the beginning address of the array located in memory 3, and the code of its volume. In the comparator 12, the codes of the first and second initial addresses of the memory 2 are entered, beginning with which the words of the array containing the "1 and" O in the second digit of the sign will be written in memory 2. In this case, the second starting address is calculated based on the number of array words calculated at the previous stage. Containing “b in the second category of the sign. The control unit 10 adjusts the block 9 of the ra: (dividing into the analysis of the second and third bits of the feature. The RDB 13 and 14 are nullified. After these preparations, the second stage of array ordering is performed. The system operates at the second stage of the ordering in the same way as In the process of ordering the second bit of a sign, the number of words in the array containing "1 in the third bit of the feature" is also counted. After the second stage of ordering is completed, memory 2 will contain an array consisting of two subarrays of words containing "I and" O in the second bit of the attribute. For the complete ordering of the initial array, as many ordering steps are needed as the bits have the feature by which the ordering takes place. In this case, the ordering procedure is applied every time to the array, partially ordered in the previous stage. Finally, the emphasis will be placed in the decreasing order of the attribute code, the array of information will be located in memory 2 or memory 3, depending on whether the number of bits contains an even or a correspondingly odd number of digits. Similarly, the ordering of an array in the order of decreasing the attribute code can be ordered in the array in order of increasing the attribute code of its words. The storage unit in the proposed ordering system can be executed on a memory with a large information volume, for example, on magnetic disks or drums, therefore with the help of this system one can organize arrays of information of arbitrarily large size. The proposed system can be introduced as an integral part of the data processing system, in which it can relieve the central processor of the frequently encountered procedure for ordering large amounts of information. Taking into account the technical implementation and the saving of computer time given by the system, we can consider that its use is expedient.

Claims (2)

8 The claims The information ordering system comprising a memory block, the first and second clock outputs and information input and output of which are connected respectively to the first and second clock signals inputs and the first information output and switch input, the array splitter whose first input is connected, the second information output of the switch, the control unit, the first input-output of which is connected to the control input-output of the array separation unit, and the second output of the control unit is connected to the control A switch input, characterized in that, in order to increase speed, it contains the first and second comparators, the first and second buffer storage blocks, the OR element, the first and second outputs of the switch clock signal being connected to the corresponding inputs of the first and second comparators, the control inputs-outputs of which are connected respectively to the third and fourth inputs-outputs of the control unit, the output of the first comparator is connected to the second input of the array separation unit, whose information output connected to the information inputs of the first and second buffer storage blocks, the first and second clock inputs of which are connected to the corresponding clock outputs of the corresponding array splitter and second comparator, the extreme state outputs of the first and second buffer storage blocks are connected to the corresponding inputs of the control unit, and their information outputs through the OR element - with the second information input of the switch. Sources of information taken into account in the examination: 1.Papernov A. A., Podymov V. Ya. Methods of ordering information in digital systems M., Nauka, 1973. 2.Patent of France No. 2052292 cl. G 06 F 15 / 00,1971.