SU1508219A1 - Device for controlling information exchange - Google Patents

Abstract

The invention relates to computing and is intended for use in asynchronous computing systems in which independent access is made to common multi-compartment memory from sources and receivers of information. The aim of the invention is to increase speed. The device contains a group of memory blocks, a data switch, an address switch, a memory block select switch, an encoder, an adder, a memory block select counter, an occupation counter, an input address counter, an output address counter, two flip-flops, two groups of I elements, two element AND, five elements OR, element NOT. 1 il.

Description

The invention relates to computing and is intended for use in asynchronous computing systems, in which independent access is made to the common multi-compartment memory from sources and receivers of information.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional diagram of the device.

The device contains (Fig. 1) input 1, a clock input 2 of the input feature, input 3 of the input end attribute, M-bit information input 4, where M is the input data width, input resolution 5 output, resolution output 6 setting the input flag, input 7 of the output flag, output 8 of the permission setting of the output flag, input 9 of the output end flag, P-bit information output 10, P, K 2, And 0,1,2 ..., where P is the bit output data, output 11 output resolution, the item is NOT 12, the second trigger 13, the ring shift register 14, the counter 15 input addresses, fifth element ent OR 1-6, switch 17 addresses, switch 18 memory block selector, first trigger 19, output address counter 20, second element OR 2, second element 22, fourth element OR 23, counter 24, the first element is OR 25, the first element is AND 26, the third element is OR 27, the counter 28 is the selection of the memory block, the second is the group of elements AND 29, the adder 30, the encoder 31, the first group of L elements And 32, the data switch 33 and L blocks 34 memory, each of which contains K memory nodes.

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The device works as follows. At the initial moment, the flip-flops 13 and 19 are installed, the counters 15, 20, 24 and 28 are in zero state, the ring shift register 14 is in the state of single potential at the first output and zero in all other K-1 outputs (chains installed on the diagram are not specified). In this case, at the outputs 5, 6 and 8 of the device, zero levels are formed, allowing access to the device. Setting the counters 24 and 28 to the zero state leads to the output of the outputs of the adder 30 of zero codes, while a single signal is generated at the zero output of the encoder 31, which transforms the binary code-to unitary, which sets the recording mode in the first block 34.1 memory during operation

put positive pulses on

1 input 1 device.

Information input into the device is made by M-bit words, and information output is made by P-bit words, and M MHK, where K 2, H O, 1,2, ... Control, input and output processes with the clock frequency at the input, with 1 — input, with O — output.

If there are 34 free memory blocks (the output potential of the device is zero), the input information is set on the information input 4, and the input -2 is set to input. a negative negative signal is applied, the duration of which is equal to the data writing cycle in the memory block 34. At the moment of action of the strobe signal of the input feature at the input 2, the trigger 13 is set to one state. In this case, a single signal is formed at the output 6 of the device, which prohibits changing input information and setting the next strobe signal of the input feature. If the strobe signal of the input feature is generated at the beginning or middle of a single write pulse at the input or during the pulse of the reading (zero signal) at input 1, then the trigger 13 is set to the zero state by the negative clock front, When On this output 6 of the resolution of the installation of the sign of the year, a zero potential is formed, allowing a change in9. four

the formation at input 4 and the installation of the next gating pulse at input 3, and the falling edge of a single signal from the output of the trigger 13 is shifted in the ring shift register 14, which specifies the node (34.1.1 - 34.1.K) of the memory into which information at this address of the first memory block 34. If the strobe signal of the input feature is generated during a negative differential on the clock input, then the setting of the trigger 13 to the zero state is realized by the negative edge of the clock pulse following the end of the strobe signal of the input feature.

The duration of the signal at the resolution inputs of the memory 34 is determined by the duration of the pulses at the input 1 of the device and at the output of the trigger 3 and in any case cannot be less than the duration of the input indication signals determining the duration of the recording cycle.

The number of bits of the ring shift register 14 is equal to K, with a single signal at each time point can only be formed at one output, therefore during positive pulses at the input 1 of the device, the resolution signal can only be sent to one of the K nodes 34.1.1- 34.1. To the memory of the first memory block 34. Each memory block 34 contains. To each of the memory nodes of the size M each, an infermation record to the nodes 34.1.1-34.1. K during the input cycle is made through the switches 33.1-333 K of data alternately according to the enable signals from the switch output. 18. When information is written at this address in node 34.1. A single signal is generated at the K-output of the ring shift register 14, the falling edge of which increases by one the contents of the counter 15 of the input addresses. In this way, the following M-bit word will be written to node 34.1.1 of the first memory block 34, but at the following address,

At the time of the end of the cycle of writing the array to the first memory block 34 at input 3, a signal of the end of input feature is generated, which increases the content of the busy count 24 by one. This leads to the following data array in loops

the input will be recorded in the second — memory block 34, since a single signal in the input cycles will be generated at the second output of the encoder 31,

If the length of the array being written is greater than the capacity of one memory block ff, then at the moment of filling the capacity of one memory block 34 at the output with a overflow, all the K nodes 34 of the selected memory block simultaneously read information to the output 10 of the device. In this case, the data is gated with a signal from the input 7 of the device. The falling edge of the trigger signal 19, the content of the counter 20, which specifies the output address of the memory block 34, changes

On counter 15, a signal is generated, Q per unit. The presence of a single signal through the element OR 23 enters the input of the counter 24 and increases its contents by one. In case of equal length of the recorded array and the capacity of the memory block 34, in order to avoid double operation of the counter 24, input 3 is blocked by forming a zero signal at the element output W 16, arriving at the second input of the element And 22, Employment of at least one memory block 34 with an array of data is characterized by the presence of a single signal at the output 11 and indicates the need to output data from unit 34 memory.

The data output process is as follows.

During the output cycle (zero input signal l), the data outputs in the Full To nodes 34 of this memory block are connected via switches 33.1-33 to the output 10 of the device. The outputs of the And 29 element are blocked, therefore the number of the memory block 34 is determined by the counter code 28. After writing the data array to the first memory block 34, the zero code will be sent to the inputs of the encoder 31 in output cycles, t, e. the output will be made from the First Memory Block 34. At the time the signal arrives at input 7, the flip-flop 19 is set to one state. If the output attribute from input 7 of the device enters in the middle of the cycle (or input), then flip-flop 19 is reset by the falling edge of the output signal, if the output flag arrives at the moment of mode change, then flip-flop 19 is triggered by the falling edge of input 1, next after the termination of the signal at the input 7 of the device.

The impulse from the trigger output 19 goes to the first inputs of the switch 18 and during the output cycle, a resolution signal is applied to all the K inputs of the memory block 34 during output cycle, thus setting output 8 at the output to prohibit the installation of the next output indication signal at input 7,

At the time of the end of the data output

t5 from this memory block 34, input 9 receives a signal increasing the contents of counter 28 and decreasing the contents of counter 24 by one. That means reading the following

The array 20 will be implemented from the next memory block 34. If the length of the output array is greater than the capacity of one block 34, then at the moment of overflow of the capacity of counter 20, a signal is generated at the end of overflow of this counter, which changes the contents of counters 24 and 28. If all the memory blocks 34 are occupied, then the counter overflow output 24

3Q (output 5 of the device) a signal is generated which will prevent the input of the next data array, as long as at least one memory block 34 is not available. The capacity of the counter 28 is equal to the number of memory blocks 34. After reading the data array from the last block 34.A, the counter is reset to zero. 28, e, the next data array will be read from the first memory block 34.1.

35

40

The adder 30 is performed as follows. If the number of memory blocks is 34

 H

45

50

55

is a multiple of Z, where H l, ii, J ,,, j then the cytmator 30 is a modulo-two adder. In general, the summation module is determined by the number of memory blocks 34. For example, for ten memory blocks 34, adder 30 is a ten-day clock.

Claims (1)

Invention Formula A device for controlling the exchange of information, contents; its group of memory blocks, data switch, adder, encoder, memory block selection counter, busy counter, input address count, address count, and one unit. The presence of a single signal at the output 8 serves as a prohibition of the installation of the next signal of the sign of the output at input 7, At the time of the end of the data output From this memory block 34, input 9 receives a signal increasing the contents of counter 28 and decreasing the contents of counter 24 by one. That means reading the following The array will be implemented from the next memory block 34. If the length of the output array is greater than the capacity of one block 34, then at the moment of overflow of the capacity of counter 20, the output of the overflow of this counter is formed by a signal that changes the contents of counters 24 and 28. If all the memory blocks 34 are occupied, then the output of overflow of counter 24 (output 5 of the device) a signal is generated that prevents the input of the next data array, so that at least one memory block 34 is not released. The capacity of the counter 28 is equal to the number of memory blocks 34. After reading the data array from the last block 34.A, the counter is reset to zero. 28, t, e, the next data array will be read from the first memory block 34.1. The adder 30 is performed as follows. If the number of memory blocks is 34  H five 0 five is a multiple of Z, where H l, ii, J ,,, j, then cytimator 30 is a modulo two adder. In general, the summation module is determined by the number of memory blocks 34. For example, for ten memory blocks 34, adder 30 is a ten-day clock. Invention Formula A device for controlling the exchange of information, contents; its group of memory blocks, data switch, adder, encoder, memory block selector counter, load counter, input address counter, output address counter, address switch, two triggers, five elements {SHI , two elements AND, the element is NOT, and the groups of information inputs and outputs of the data switch form groups of inputs and outputs of the device to connect respectively to the groups of information outputs and inputs of a computer, the output of the counter overflow is output The device for connecting to the input of the computer input permit, the output of the first element OR is connected to the information input of the first trigger and is the output of the device for connecting to the computer output enable input, the output of the second trigger is the device output for connecting the input input of the computer input attribute setting, the output of the first trigger is connected to the counting input of the output address counter and is the output of the device for connecting to the enable input of the installation of the computer output feature, the first input of the first element I is with the input of the device for connecting the output terminal of the computer to the output, the first input of the second element I is connected to the installation input of the input address counter and is the input of the device for connecting the output end of the computer to the output of the computer, the input of the element is NOT connected to the zero input of the first trigger, address switch input, with the data switch control inputs, with the read and write entries of the memory blocks of the group, and is the device input for connecting to the clock output of the computer, the single input of the second trigger and the sync the input of the first trigger are the inputs of the device for connecting, respectively, to the output of a sign of a computer input and to the output of a sign of a computer output, while the groups of information inputs-outputs of the data switch are connected to the formation inputs-outputs of the memory blocks of the group the information output of the address switch, the first group of information inputs of which is connected to the output group of the output address counter with the input group of the second element OR, the output of which is connected to the second in the course of the first element And, the output of which is connected to the first input of the third element OR, the output which is connected to the 9th subtraction input of the occupation counter and to the counting input of the selection counter of the memory block, the output group of which is connected to the first group of information inputs of the adder, the information output group of which is connected to the group of information inputs of the encoder, the group of inputs of the first element OR occupation, the input of which is connected to the output of the fourth element OR, the first input of which is connected to the output of the second element AND, the second input of which is connected to the output of the fifth the OR element, whose input group is connected to the second group of information inputs of the address switch and the output address counter output group, the overflow output of which is connected to the second input of the fourth OR element, the second input of the third CM element is connected to the Output address counter overflow output, the element output is NOT connected With the left input of the second trigger, characterized in that, in order to improve speed, a ring shift register, a switch of the selection of the memory unit, two groups of elements I, with this the volume is permitted to the inputs of the group's memory blocks connected to the corresponding outputs of elements AND of the first group, the first inputs of which are connected to the corresponding outputs of the encoder, the bit inputs of elements AND of the first group are connected to the corresponding discharge outputs of the memory selector switch, the control input of which is connected to the first inputs of the elements of the second group and with the control input of the address switch, the output of the first trigger is connected to the first group of information inputs of the memory block selector switch, the second the group of information inputs of which is connected to the group of outputs of the ring shift register, the output of the higher bit of which is connected to the counting input of the input address counter, the installation input of which is connected to the installation input of the ring shift register, the shift input of which is connected to the output of the second trigger and the second inputs of the AND elements the second group, the third inputs and outputs of which are connected915P821910 yens, respectively, with the group of the outlet, the installation input of the counter The number of output addresses is connected to the first input of the first element I. .m Yu The output addresses are connected to the first input of the first element I.