SU1529435A1 - Pulse sequence selector - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automatic navigation and radar control systems for extracting pulses following an interval multiple of a predetermined value. The purpose of the invention is to provide the possibility of separating pulse sequences with intervals between pulses that are multiples of a given value, as well as ensuring a given noise immunity. The selector contains input 1 and clock 2 tires, elements 4 and 14, counters 5, 7 and 9 pulses, memory block 6, output 15, and mounting 18 tires. The goal is achieved by introducing the element HE 3, the code setting units 8 and 11, the comparison blocks 10 and 13, the counters 12 and 16 pulses, the decoder 17, and the formation of new functional connections. 1 hp f-ly, 2 ill.

Description

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The invention relates to a pulse technique and can be used in automatic navigation and radar control systems for extracting pulses following an interval multiple of a predetermined value.

The purpose of the invention is to provide the possibility of separating pulse sequences with intervals between pulses that are multiples of a given value, as well as ensuring a given noise immunity.

FIG. shows the electrical structure of the device; in fig. 2 is a numerical diagram explaining the operation of the device.

The device contains an input bus 1, a clock bus 2, which is connected to the input element HE 3, the output of which is connected to the second input of the first element I 4. The cycle bus 2 is connected to the subtraction input of the first pulse counter 5, the outputs of which are bitwise connected with the address inputs of the memory block 6, the data outputs of which are bitwise connected to the information inputs of the second counter 7 pulses. The device also contains the first code setting unit 8, the borrowing output of the counter 5 is connected to its own input 1 (the recording and counting input of the third counter 9 pulses, the outputs of the counter 7 are alternately connected to the inputs of the first group of inputs of the first comparison unit 10. Information inputs of the fourth reference unit 10. pulse counter 12 is connected bitwise with the outputs of the second code setting unit 11, and outputs are bitwise connected to the inputs of the first group of inputs of the second comparison unit 13. The output of the control unit 10 is connected to the first input of the second element I 14, the output of which with the output bus 15. The output of the code setting unit 8 is bitwise connected to the information inputs of the fifth counter of 16 pulses, the outputs of counter 9 are bitwise connected to the inputs of the decoder 17, and the information inputs of the counter 5 form the installation bus 18. The cycle bus 2 is connected with the write input of counter 7, the counting input of which is connected to the output of element 4 I, the reset input to the output of the decoder 17 and the write inputs of counters .12 and 16, and the outputs

bitwise with the inputs of the second group of inputs of the comparison unit 13, and also bitwise with the data inputs of the memory unit 6, the recording entry of which is connected to the second input of the And 4 element. The first input of which is connected to the second input of the And 14 element and the input bus 1. The input resetting the pulse counter 9 is connected to the output bus 15, the output of the comparison unit 13 is connected to the counting inputs of the counters 12 and 16 pulses, and the outputs of the counter 16 pulses bitwise are connected to the inputs of the second group of inputs of the comparison unit 10.

The digital diagram (Fig. 2 in the left column shows the numbers of the cycles N of the pulse sequence arriving at the selector bus 2. The value of N is counted from the moment of setting the selector to its original state. Each beat is divided into two half-pulses: negative (zero) and positive (single This is possible as a result of the arrival of a signal of a meander type on bus 2. The top line contains the element numbers of the device components. The chart field is composed of numbers defined by code combinations at the outputs corresponding to elements N at selected times.

Before starting, using block 1 and 8 of setting the codes, two threshold levels are set, respectively, L, and the M-decoder is set to a given number 17. The number M is chosen from the condition

P (T, M c J P,

T (; is the interval between two adjacent pulses in the sequence of useful signals, which is generally random and a multiple of a known value of 5, PJ is the given probability of detection and selection of useful signals.

Absolute values

B, „„ not

have a significant effect on the noise immunity of the device, but their difference (L - b „„) affects the noise immunity, so it must be greater than the number of distortions

one element of the pulse sequence per observation interval

a, - ü „,) to.

The set values L, and "," are recorded in the counters 12 and 16 by the initial setup signal generated at the output of the decoder 17. The condition for the formation of this signal is the absence during the MT time of the useful signal at the input bus

1 selector. The installation siggtalsm zeroed out memory block 6 by writing in its cells a zero code combination from counter 7, the reset input of which is connected to the output of the decoder 17. The subtracting input of counter 5 receives pulses from the clock bus

2 selectors. The credit output of the counter 5 is connected to the recording enable input of the same counter. As a result, a nulling signal at the output of a loan of counter 5 appears every 9 pulses of a clock sequence (where P is the code combination at the information inputs of counter 5, forming the installation bus 18).

The value ® is chosen from the condition

0 G-,

Where

Ggi pulse frequency on the clock bus 2 selector.

This leads to the fact that through time, multiple, code combinations at the output of the counter 5 will be repeated. The outputs of counter 5 are connected to the address inputs of memory block 6, which consists of 0 R-bit cells. The number of the polled cell is determined by the code combination at the outputs of counter 5. As a result, each cell is polled after 9 cycles, i.e. with a period of T g.

In turn, by polling a cell, it is meant to rewrite its contents into counter 7 under the influence of a clock pulse. If during the interrogation of a cell, a signal is present on the input bus 1 of the selector, then after the end of the clock pulse (in the second half of the half-cycle) 1 from the output of the element NO 3, it passed through

five

cell of block 6. Otherwise, i.e. in the absence of a signal on the input bus I of the selector, the content of the polled cell remains unchanged.

Thus, the contents of the cells of the memory block 6, the polling instants of which coincide with the moments of arrival of signals on the input bus 1 of the selector, are increased by one. And the more often such coincidences occur, the faster the contents of the corresponding cells will grow.

If the intervals between the pulses of the input realizations are uncorrelated with the polling period of the cells of the memory block 6, then these pulses will coincide with equal probability with the interrogation points

0 any cells of this unit.

If the intervals between the pulses of one of the signals on the input bus 1 turn out to be multiple to the polling period of the cells of memory block 6, then the arrival times of these pulses always coincide with the moments of polling of the same cells of block 6. This leads to the contents of these cells increases much faster

0 than all the others. During the polling process, the content of each of the cells is compared with the number recorded in the counter 12. When this value is reached, a pulse appears at the output of the comparison unit 13, which, entering the counter input of the counter 12, increases its content by one. The same impulse increases by one and the number recorded in the counter 18. Thus, the content of any of the cells cannot exceed the number recorded in the counter 12. The rate of change of this number corresponds to the rate of change of the number in the cell with the maximum content, i.e. that cell, the polling moments of which coincide with the moments of the arrival of the useful signals on the input bus of the selector. The numbers, written 1n in counters J6 and 2, change at the same speed, but the number in counter J6 is always less than the number in counter 12 by the value ().

At the output of block 10, comparison 1

five

0

ment And 4, increases the contents of the score-55 appears only in the case when

Chika 7 per unit. Under the action of the same logical unit, the increased by one unit the contents of counter 7 is rewritten - back into the opr shivaemyk

the content of the polled cell is greater than the number recorded in counter 16. If 1-1 tons of n is slightly less than L, 1 at the output of the comparison unit 10, the matched content of the polled cell is greater than the numbers recorded in counter 16. If 1-1 tons of n is slightly less than L, 1 by the output of the comparison unit 10 coincides with the arrival time of the pulses of the useful signal on the input bus 1 of the selector. These pulses and pass through the element And 14 on the output bus 15.

Thus, from the input of the selector output bus 15, only impulses of useful signals pass from its input. These pulses systematically embed counter 9 and do not allow a number greater than M to accumulate in it.

In the absence of a useful signal on the input bus 1 of the selector, the systematic resetting of counter 9 stops and the number accumulated in it as a result of the zeroing signals from the counter output of counter 5 reaches its value M. As a result, the output of the decoder 17 generates a signal initial setup that brings the device back to its original state.

According to the principle of operation of the device on a specific example using a numerical chart (Fig. 2). Suppose that 0 19, M 15,

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The numerical diagram shows only those clocks during which the input bus J received either the signals of the useful signal or interferences. Suppose that during the fifteen previous polling periods there were no useful signals on the input bus 1 of the selector. Therefore, on the 303rd () clock, the selector is reset to the initial state. After this, the first impulse of the useful signal arrives at the selector bus 1 during the 4th, 5th and 6th cycles and coincides with the polling points of the 4.5th and 6th cells of the memory block 6. The second, third and fourth signal pulses, respectively, coincided with 6J, 62, 63, 99, 100, JOJ and 175, 176, 177 cycles, i.e. Received through a multiple of 19 the number of cycles. Moments: The positions of the second, third, and fourth pulses also coincided with the moments of the 4, 5, and 6th slots of memory 6 of the memory block. With L2, 202, and 203rd, the interference pulses on the input bus 1 coincided. In addition to the TRG, the second front pulse was distorted, and the fourth had a rear edge. Under these conditions, information accumulated faster in the fourth cell, the moments of the survey of which coincided with the non-distorted midpoint of the pulse. Under the action of the contents of this cell, a change occurred in the counters 12 and 16.

After the 99th cycle, the selected pulses of the input signal begin to pass to the bus 15 of the selector. The device is more stable if the sequence of pulses at its input is strictly periodic.

Thus, the introduction of new elements and the connections between them made it possible to isolate signals, which are a sequence of pulses with intervals between them that are multiples of a given value.

In addition, the selector has a higher noise immunity, since the decision to detect a useful signal in it is made not by two pulses, as in the prototype, but by all I pulses in a burst, i.e. signal to noise ratio at the output of the device by 1/2 time

more than in the prototype.

Claims (2)

1. The pulse sequence selector, which contains the first pulse counter, the input of which is connected to the clock bus, the information inputs form the installation bus, and the loan output is connected to its record input, the first And element, the first input of which is connected to the input bus, the second And element The output of which is connected to the output bus, as well as the memory block, the second and third impulse counters, is characterized in that in order to enable the selection of pulse sequences with intervals between pulses, multiples of the specified value, the decoder, the first comparison block, the first code setting block and the NOT element, whose input is connected to the clock bus and the second pulse counter recording input, are entered into it, and the output to the recording input of the memory block and the second input of the first element I, the output of which is connected to the counting input of the second pulse counter, the outputs of which bits are connected to the inputs of the first group of inputs of the comparison unit and also bitwise to the data inputs of the memory unit, the data outputs of which are bitwise connected to the information inputs of the second pulse counter, and the address inputs of the first pulse counter, the output of which connected to the counting input of the third pulse counter, the reset input of which is connected to the output bus, and the outputs are bitwise connected to the inputs of the decoder, the output of which is connected to the reset input of the second pulse counter, and the inputs the second group of inputs of the first block srpviyii bitwise connected to the outputs of the first block installation code, and the output is connected to the first input of the second 529.3510 element And, the second input of which is connected to the input bus. 2. A selector according to claim 1, in which, in order to ensure a given noise immunity, a second code setting unit, a fourth pulse counter Q ow and a second comparison block, as well as a five pulse counter, are inputted into it, connected between the outputs of the first code setting unit and the inputs of the second group of inputs of the second comparison unit, with the inputs of the second group of inputs of the second comparison unit being bitwise connected to the outputs of the second pulse counter, and the output with counting inputs of the fourth and fifth counting Cove 20 pulses, recording inputs of which are connected to the output of the decoder.