SU1325494A1 - Device for controlling information exchange between processor and memory - Google Patents

Abstract

The invention relates to computing and can be used to build fast memory processor systems. The aim of the invention is to increase the reliability of the device by organizing a backup of the memory. The device contains the first 1 and second 2 address counters, a command distribution block 5, a control block 6, a pulse generator 7 and a pulse distributor 8. The device provides random access memory addressing and memory backup in case of failure. 1 hp f-ly, 1 ip. CE 12 16 (L 20, 8

Description

The invention relates to computing, in particular, memory voltage devices, and can be used to build fast memory processing systems.

The purpose of the invention is to expand the functionality of the device through the organization of work with two memory blocks.

The drawing shows a block diagram of the device.

The device contains the first 1 and second 2 address counters, the first 3 and second 4 memory blocks, the command distribution block 5, the control block 6, the pulse generator 7, the pulse distributor 8, the device start input 9. Block 5 contains the trigger 10, the first 11 and the second 12 elements AND-NOT, the first 13, the third 14, the fourth 15 and the second 16 elements AND, the first 17 and the second 18 elements OR NOT, the first 19 and second 20 elements NOT, Block 6 control contains the first to the fifth triggers 21-25, the element OR 26 "The device also contains the first 27. and the second 28 switches.

The device works as follows.

The control unit 6 generates a sequence of commands implementing the algorithm (write-match) of the memory operation.

The synchronization unit 6 is carried out by the generator 7 through the distributor 8, which is a shift register, controlled by pulses from the output of the generator 7.

For the conjugation of the operating time of the triggers of the control unit 6 and the synchrums of SI1-SI4, the duration of the latter can be additionally formed by the pulse shaper on the leading edge (not shown).

A single sweep of the distributor 8 constitutes a synchronization cycle which may include a different number of clock signals, for example, four: SI1-SI4.

The information to be written to blocks 3 and 4 is associated with the trigger signal on bus 9 and, if necessary, can be synchronized with a corresponding signal from the output of block 6, for example from the trigger output 21. The trigger signal on bus 9 is used

also to synchronize counters 1 and 2..

The distributor 8 is reset when the supply voltage is applied, this state corresponds to the unit potential of the signal CI4, which sets the triggers 23 and 24 to a single position. A single potential from the output of the trigger 23 sets the trigger 25 to the zero position, which corresponds to the single potential at its inverse output.

Setting the trigger 10 of block 5 to a single position corresponds to the write mode for block 3 and the read mode for block 4. The single position of the trigger 23 of block 6 is a ban on writing to blocks 3 and 4, and the single position of the trigger

24- ban on reading information from blocks 3 and 4.

The trigger signal in the bus 9 changes the position of the trigger 10 and, thus, changes the recording modes and reads the blocks in blocks 3 and 4.

From the outputs of the generator 7, the synchronization inputs of the flip-flops 21 and 22, respectively, receive pulses of read and write frequency. Triggers 21 and 22 under the influence of pulses from the outputs of the generator 7 prepare the triggers 23 and 24 to work on SI1.

If, under the influence of pulses from the output of the generator 7, the flip-flops 21 and 22 overturn in one state, then under the influence of SI1, the flip-flops 23 and 24 are set to the zero state, and the output potential of the AND-NE element 11 is zero. in block 3. Recording occurs via SI2, which sets the trigger

25 in a single position, with the output of the OR-NOT 17 element appearing zero potential arriving at the gate input of unit 3.

Reading from block 4 occurs while maintaining a single potential at the output of the element AND-NOT 12 and the appearance of a zero potential at the output of the element OR-NOT 18, which occurs at a single potential at the inverse output of the trigger 24. Recording and reading information in blocks 3 and 4 occurs without mutual exclusion.

If in the process of operation information is received on the distortion of authenticity of information from the control unit, then this signal can be used to transfer unit 3 or 4 to work in the reserve zone, which is connected to the work by changing the potential at input A. The potential change can be performed manually using switches 27 and 28.

Invention Form

1, A device for controlling the exchange of information of a processor with a memory, comprising a control unit, a pulse generator and a distributor, with the first and fourth outputs of the pulse distributor being connected to the clock inputs of the first to fourth control units, the clock input of the pulse distributor is connected to the first output of the pulse generator, the second and third outputs of which are connected respectively to the fifth and sixth synchronization inputs of the control unit; the first counter of the address, the reset input of which is connected to the in device for connecting the processor startup output, the output of the first address counter is connected to the device output for connecting to the address input of the first memory block, which, in order to expand the functional capabilities of the device by organizing work with two blocks the memory, the command distribution block and the second address counter are entered into it, where the reset input of the second address counter and the start input of the command distribution block are connected to the device input to be connected to the processor start output The second address counter is connected to the output of the device for connecting the second memory block to the address input, the clock inputs of the first and second address counters are connected to the first, second outputs of the command distribution block, the third, fourth outputs of which are connected to the outputs of the device for connecting to the sample inputs respectively, the first, second memory blocks, the fifth, sixth outputs of the command distribution block are connected to the outputs of the device for connecting to the read / write enable inputs respectively second, second memory blocks

0

5 0 5 O 5 0 5 Q g

The first to third outputs of the control unit are connected to the resolution inputs of the first to third command distribution units, the fourth output of the control unit is connected to the output of the device for connecting to the interrupt input of the processor, the command distribution unit contains a trigger, the first, second AND-NOT elements, first to fourth elements are AND, the first, second elements are OR-NOT, first, the second elements are NOT, with the nepBbrii block enable input connected to the first inputs of the first, second AND-NOT elements, the second permission input b It is connected to the first inputs of the first, second And elements, the third input of the resolution of the block is connected to the first inputs of the third, fourth And elements, the outputs from the first to the sixth block are connected respectively to the outputs of the first, second elements of NO, first, second elements OR NOT of the first, second AND-NES elements, the start-up input of the block is connected to the trigger synchronization input, the unit output of which is connected to the second inputs of the first AND-NE element, the first and fourth AND elements, the zero output of the trigger is connected to the second inputs The second element AND-NOT, the second and third elements AND, the outputs of the first, second elements AND are connected respectively with the first inputs of the first, second elements OR-NOT, the outputs of the third,. the fourth elements AND are connected respectively to the second inputs of the first, second elements OR — NOT, the outputs of the first, second elements OR — NOT connected to the inputs of the first, second elements NOT, 2, the device pop, 1, characterized in that the control unit contains from the first for the fifth trigger and the OR element, the fifth, sixth block synchronization inputs are connected to the synchronization inputs of the first and second triggers, respectively; the first synchronization input of the block is connected to the synchronization inputs of the third and fourth trigger c, the unit inputs of which are connected to the second synchronization input of the block, the third, fourth synchronization inputs of the block are connected respectively to the synchronization input of the fifth trigger and to the first input of the OR element,

513254946

the second input and output of which connect the second flip-flop and the third output of the nena respectively with a single output unit; the information inputs of the first, the house of the fourth trigger and the fourth-fourth flip-flops are connected to the bus; the unit's output potential is zero, the third output is connected to infor - 5 zero outputs of the first, second output inputs of the fifth trigger, triggers are connected respectively to the zero input of the first trigger and to the information inputs of the third to the first output of the block, the second output and the quarter th flip-flops, a single unit connected to the output of the fifth output of the third flip-flop is connected to the trigger, the zero output of the fourth zero input O trigge- fifth latch connected to the zero input pa.

Claims (3)

Claim 1. A device for controlling information exchange of a processor with memory, comprising a control unit, a pulse generator and a distributor, wherein, from the first to fourth outputs of the pulse distributor are connected to synchronization inputs from the first to fourth control unit, the clock input of the pulse distributor is connected to the first output of the pulse generator, the second and third outputs of which are connected respectively to the fifth and sixth synchronization inputs of the control unit, the first address counter, the reset input of which is connected to the input devices for connecting the processor start-up output, the output of the first address counter is connected to the device output for connecting to the address input of the first memory block, characterized in that, in order to expand the functionality of the device by organizing work with two memory blocks, a distribution block is introduced into it commands and a second address counter, wherein the reset input of the second address counter and the start input of the command distribution block are connected to the input of the device for connecting to the processor start output, the output is second of the address counter is connected to the output of the device for connecting to the address input of the second memory block, the clock inputs of the first, second address counters are connected respectively to the first, second outputs of the command distribution block, the third and fourth outputs of which are connected to the outputs of the device for connecting to the sampling inputs, respectively, of the first , the second memory blocks, the fifth, sixth outputs of the command distribution block are connected to the outputs of the device for connecting to the read / write permission inputs, respectively, of the first, second of the first memory blocks, the first to third outputs of the control unit are connected to the resolution inputs, respectively, from the first to the third command distribution unit, the fourth output of the control unit is connected to the output of the device for connecting to the processor interrupt input, and the command distribution unit contains a trigger, first, second elements AND NOT, the first to fourth elements AND, the first, second elements OR-HE, the first, second elements NOT, and the first input of the block permission is connected to the first inputs of the first, second elements AND, NOT, the second the block enable input is connected to the first inputs of the first, second AND elements, the third block enable input is connected to the first inputs of the third, fourth AND elements, the outputs from the first to the sixth block are connected respectively to the outputs of the first, second elements NOT, the first, second OR-HE elements , of the first, second AND-NOT elements, the start trigger input is connected to the trigger synchronization input, a single output of which is connected to the second inputs of the first AND-NOT element, the first and fourth AND elements, the zero trigger output is connected to the second E inputs of the second AND-NO element, second and third AND gates, outputs of the first, second AND gates respectively connected to first inputs of first, second OR-HE, third outputs. the fourth AND elements are connected respectively to the second inputs of the first, second OR-HE elements, the outputs of the first, second OR-HE elements are connected to the inputs of the first, second elements NOT. 2. The device according to claim 1, characterized in that the control unit comprises first to fifth triggers and an OR element, the fifth and sixth synchronization inputs of the block being connected to the synchronization inputs of the first, second triggers, the first synchronization input of the block is connected to the synchronization inputs of the third and the fourth trigger, the single inputs of which are connected to the second input of the synchronization block, the third, fourth synchronization inputs of the block are connected respectively to the synchronization input of the fifth trigger and the first input of the And element LI, the second input and output of which is connected ¹ with the single output of the fourth trigger and the fourth output of the block, the zero output of the third trigger is connected to the information input of the fifth trigger, with the zero input of the first trigger and the first output of the block, the second output of the block is connected to the output the fifth trigger, the zero output of the fourth trigger is connected to the zero input of the second trigger and to the third output of the block, the information inputs of the first, second triggers are connected to the unit potential bus of the device, 5, the zero outputs of the first, second triggers are connected respectively to the information inputs of the third and fourth triggers, the unit output of the third trigger is connected to the zero input of the fifth trigger.