SU525939A1 - Device for interconnecting communication processor - Google Patents

Description

(54) A DEVICE FOR PAIRING THE EXCHANGE PROCESSOR WITH THE SECHI CHANNELS irip.i, gosinrnogo / 1v ((:.- Tauk. I 1114 dash nninu ix, register 1x1, and find out how to make a table and find out how it’s used to make it work. : t1; tp () but having secured T T by, m ((x: t sent with communication channels, which kkch-h tat on bytes or bypassing avlein) hedgehog, them; or) bsti. The volume of the information HI.IX arrays of the HI.IX arrays cannot be distributed with a nail before the discharge, which is not always convenient from the point o} 1 of their further processing ;; the demand for the service generated after the end of the exchange of a given data array does not cause P1) the jHpotpaMMbi process of the processor, but is polled by the program, which increases the response time to this requirement. This device uses an address counter and an information array length counter, which increases the device hardware o6iieM. The purpose of the H3o6j5eTeHMH is to increase the productivity and increase the utilization rate of the equipment of the device. This is achieved due to the fact that the subscriber's address encoder is entered into the device, control units for random exchange, control of the counting input, exchange of bytes and exchange of service signals, the control inputs of which are connected to the corresponding outputs of the central control unit, and its input connected to the output of the unit sharing the slopes with ebnymi signals. Input and; ifrator address is connected to the third output of the communication unit with the channels, output - to the input of the exchange processor. A control unit for data exchange is connected by two-way links with a data register and a communication unit with channels and connected by input X to a second output of a data counter, two inputs of which are connected to the corresponding outputs of the control unit of the counting input. The second output of the register of service. Signs of the connection with the input of the control unit of the counting input, the units for exchanging bytetaml and exchanging service signals are connected to communication channels, the unit for exchanging bytes with two-way communication with the register yes. The data counter contained in ycTfX ii is not only (it counts the number of Hf.ix information quanta, but also executes the counter of the on-line memory (RAM) address counter. iia drawing device diagram. It contains zeitral. Lazy block 1 yiiiRiv, block 2 communication with channels, include 1 al example of the three exchange modules 2 2,; block 3; luzheb i., cnruiUiaMi 1 1if {{4 torus 4 subscribers, register G: on the subscriber state, registrar G, data). switch 7, block 8 management. :: m; eii porp:;. ds, 1m sdmioiok., byte exchange unit 9, register 1O of services (sign, block i, counting input, count 12 n i1x, decoder ITi, shaper 14 RAM, exited 15-19, 20p2 () and inputs 21-23, 24, 25 25j devices, the structure of the yugistra 5 words, the number of subscribers, 6 registers 6, K) counter 12 data. The device works as follows o6pa30Ni. At the entrances 25.-. 25 devices and then to the inputs of the communication unit 2 with the channels during the discharge of the exchange with the communication channels, information sequences of 1 pulses are received, and to the inputs of the device -. clock sequences. For each clock pulse, the channel communication unit 2 memorizes the information bit and issues a service request to the central control unit, which, if it is not engaged in servicing other requirements, samples the service request. The sampling signal from the output of the central control unit 1 is fed to the input of the 2c communication unit from the channel and passes sequentially through all the modules 2, - 2 of the communication unit 2 with the channels. The first module, which issued the exchange request, blocks the further passage of the sampling signal and outputs the ready-to-work signal and the subscriber's address from its output to the central control unit through the signaling exchange circuit. When the ready-to-work signal is received, the central control unit 1 controls the reading of the subscriber state word (villages) from the operational memory (RAM), which from the input 21 through the switch 7 follows the signal from the output of the central control unit 1 the input of the switch 7 is recorded in the register of 10 service signs and the counter 12 dant) x. The service attribute register 10 contains the indication of the exchange direction, the control indication, the indication of the exchange of bytes, which from the output of the service characteristics register arrive at the input of the central control unit 1. Counter 12 indicates the number of information quanta (bits, bytes) that need to be exchanged with a communication channel on a given SSA. With a one-by-one exchange, the control and byte exchange characteristics are zero. The address of the RAM cell, from which the readout of the SSA is ocyniecTi, is determined by the output memory code 14 of the RAM address, which forms it in accordance with

“-JfCTBHH with GM ao} ient, pic g y11ai. to the input .РОЕ-atel 1А hell) wasp from the output of block 2. In the device for each aboneite, there is a fix about Ea in the RAM area, which is split-to-two into two zones. HONE ia code submarine operation in the KawiOM module of the communication unit 2 with channels

After reading the SSA, the central block i of the module is read the data byte from the RAM, which is written to the data register 6 through the switch 7. The data storage address is determined by the memory address maker 14 in accordance with the subscriber address received at the input of the imaging unit 14 and the old bits - 1 of the data counter 12, coming from the output of the latter to the input of the imaging unit 14 of the operative address.

When the fio signal is input, nocTjTiaromeMy from the output of the central control unit 1 to the input of the bit-exchange control unit 8, the information bit from the communication unit 2 with the channels through the bit-exchange control unit 8 is recorded into the corresponding data register 6. The bit number of the data register is determined by the value of the three lower bits of the data counter 12, the signals from the output of which are posukkggy to the input of block 8 of the control by bit exchange. Then

the contents of the register 6 through the switch 7 from the output 15 of the device is written to the RAM.

At the end of the exchange cycle with one of the modules of block 2, the signal coming from the output of the central control unit 1 to the input of control unit 11 of the counting input, the latter generates a signal that goes from the output to the input of data counter 12 and counts the unit from the counter data. If the content of the counter becomes equal to zero, then the decoder 13, to the input of which the value of the data counter arrives, outputs from the output a signal to the input of the central control unit 1, at which the last Eir) abat the signal at one of the outputs. According to this signal, the encoder 4 of the subscriber's address generates an interrupt code from the output, which from the output 17 of the device enters the system of interruptions of the primary distributor in accordance with the address of the subscriber received at the input of the encoder 4.

In addition, the central control unit 1 generates a signal for changing the number of a subzone that is sent along the circuit by control signals to the communication unit 2 from the channel. Then, the SSA is written to RAM through switch 7.

The method of exchange with a bitwise output is denied by the fact that the sequence of clocks. 1x impulses of the communication path to the inputs 24. the device reads the information symbols, which from the outputs 2O - 2O of the device enter the communication channels. In addition, after reading the data byte of the RAM into the data register 6, the contents of one of the bits of the data register 6 are processed through the nopjaa exchange control unit 8 to the corresponding module of the block 2. The output of the output data register 6 is also defined as at the bottom of the input.

When exchanging the bytes, input or output requests are sent to the device inputs 24 to 24, by which the communication unit 2 with the channels issues a service request to the central control unit 1. After being sampled by the central control unit of the subscriber, it stops reading from the RAM, SSA and data byte. At the same time, in the register of 10 service digits, the byte exchange indicator is equal to one, and therefore the signal from the output of the central control unit & laziness, which enters the input of the byte exchange unit 9, produces a byte from the data register 6 through the byte exchange unit 9 and output 19 devices to communication channels. A byte datyy gh is accompanied by a dangal sign issued to the communication channels from the service signaling exchange unit 3 when the last signal arrives from the output of the central control unit 1. In addition, an appropriate exchange is allowed to the communication channels from the corresponding module; After receiving a byte, the dan-channel generates a signal about it, which, with INPUT 22 of the device, without signal exchange unit 3, is fed to the input of the central control unit 1.

According to the sTONty signal, the central control unit 1 terminates the exchange cycle with the given communication channel as well as during a single exchange. The difference is that the counting control control unit 11 subtracts eight from the data counter 12, sending a signal to the input of the data counter.

When you enter data bytes, it enters the input of block 9 of byte exchange, and then into data register 6, after block 2 gives permission to exchange to the appropriate communication channel in response to a clock pulse from a communication channel.

Claims (1)

The control of the communication channel operation modes is performed when the CCA is considered to be from the RAM when servicing the requirements from block 2, which is a sign of simplification. In this case, irrespective of how quanta information quanta are exchanged: with the communication channel, the channel. The control byte is emitted from data register 6 through block 9 by exchanging Q bytes to output 19 of the device. At the same time, via the signal exchange unit 3, a control indicator is issued / by which the corresponding communication channel receives the data byte as a control channel and produces a change in the operation mode (transition from transmission to reception, change of transmission speed, shutdown, etc.). ). The exchange of information with the communication channel can be preceded by one control byte, therefore after issuing the control byte, the control sign in the register 10 of service signs by the signal from the output of the central control unit 1 is set to zero, and the exchange requirement stored in block 2 communication with channels, not quenched. Further, the data exchange described above is carried out. In the event that during the sampling of the service requirement, sampling for some reason does not occur, the sampling signal from the second output of the communication unit 2 with the channels enters the input of the central control unit 1, sets the last and initial state. Formula of invention. A device for interfacing an exchange processor; with communication channels, containing a central control unit, in the inputs of which are connected respectively to the control inputs of the communication unit with channels, the communicator, the register of service signs, and the inputs to the first and second outputs of the communication unit with channels, the first output of the register service signs and the output of the decoder, the input of which is connected to the first switch of the data counter and the pen ;. The driver of the forger of an agus.: - A single .wti, whose input is connected to the first Bbfxf device, the second input - to the output output of the communication unit with the channels, connected with the information input and output control ports and the control input with communication channels, input and the second The output of the device is 5oot Twektochnik to the input and output of the switch, which connects two-way communication with the dongle register, the register of service signs and counting: K. data, characterized in that, in order to increase productivity and increase the utilization rate of device, entered into the subscriber's address coder, bit exchange control units, shadow control, counting input, exchange of bytes, and exchange of service signals, the control inputs of which are connected to the respective intercoms of the central control unit, the input of which is connected to the output of the exchange unit service signals, the address of the address coder is connected to the third output of the communication unit with the channels, the output to the input of the exchange processor, the control unit of the bit exchange is connected to the external connection with the data register and b eye communication with the channels and connected to the second input of the output data counter two inputs of which are connected respectively to the outputs stvuyuschim-counting input of the control unit, the second output register SLE. The signs are connected to the input of the control unit for the counting input, the blocking bytes and the exchange of service signals are connected to the communication channels, the byte exchange unit is connected by two-way links to the data register. Sources of information taken into account during exaertize: 1. US Patent No. 3720920, class 34a.172.5 (& O6 t C / GS) March 13, 1973. 2 Technical specification TU1,700.009 TOZ, revision 2-74. The interface unit with communication channels, p. 9.96.