SU849191A2 - Data interchange device - Google Patents

Description

I

The invention relates to computing and can be used for interfacing with a multiplex 1M channel of a digital computer of subscribers, which differ from the data format received in the channel and exchange with the channel containing information containing check bits.

According to the main atv.sv. No. 528561, a device for exchanging information is known, comprising a receiving node, the output of which is connected to the first input of a buffer register connected by a second input to the first output of the reception and output control unit, and the output by the first input of the output node whose second input is connected to the second output of the control unit receiving and issuing, and the first output with subscribers, the mode trigger, the output of which is connected to the first inputs of the receiving control unit and the remote control and the receiving node, the third inputs of the buffer register and the output node, the block

communication with the channel, mode analysis unit, output counter, load register, reception counter, communication unit with subscribers, with the inputs of the communication unit connected to the first output of the mode analysis unit, the third output of the reception and output control unit, second output the output node, the output of the output counter and the channel, and the outputs, respectively, with the first input of the mode analysis unit, the second input of the receiving node and the second input of the reception and output control unit, the input of the mode analysis unit is connected to the fourth output

15 of the reception control unit and at the output, and the output with the mode trigger input, the output of the output counter is connected to the fifth output of the reception and output control unit, and the output with the second input,

20 of the communication unit with subscribers and the fourth input of the delivery node, the inputs of the load register are connected respectively to the second input of the communication unit with the subscribers, the fifth output of the reception counter and the output of the mode trigger, and the output with the fourth input of the reception control unit and the reception counter connected to the sixth output of the reception and output control unit, and the output to the fourth input of the buffer register; the third input of the communication unit with subscribers is connected to the seventh output of the reception and output control unit; the output of the communication unit with subscribers n to the third input receiving a control unit and issuance, the first input unit communicating with the subscribers and a third input receiving node connected with subscribers SE

The disadvantage of the known device is the low reliability of the exchange, since the exchange of data words of different formats between the digital computer channel and the subscribers is carried out without check bits, and when matching the formats of the check bits are lost,

The purpose of the invention is to increase the reliability of the exchange.

The goal is achieved by the introduction of a block forming the control bit, a modulo-two control unit and a check-bit converting unit, the first inputs of the modulo-two control unit and the control bit forming unit being connected to the first input and output of the buffer register, the second inputs with the output of the mode trigger, and the outputs, respectively, with the first and second inputs of the control bit conversion unit, the third input and output connected to the fourth and pvym inputs of the node issue.

In this case, the control bit conversion block contains a trigger, single and zero inputs connected respectively to the first and third block inputs, and element 2I-OR-NOT, the first two inputs of which are connected respectively to the second block input and zero trigger output, the second two inputs - with a single output trigger and through the element NOT with the second input of the block, and the output with the output of the block.

The proposed technical solution allows for the exchange of multi-format data with control bits in syllables with simultaneous control of modulo-two information in the device. The subscriber (DVR} - the receiver of information when receiving data controls modulo two. In this case, the exchange of syllables with control bits, control modulo two, and the formation of control bits are performed as follows. The input syllable information (byte,

the symbol is modulo-two and is compared with the check bit received in syllable format. In the case of Norma, a normal discharge is produced in the format of the output syllable and sent to the subscriber or to the channel. In the case of Reject, the check bit in the output syllable format, formed from the contents of the syllable with an error, is converted into an inverse value (distorted) in order to detect an error by the subscriber (DVM), the receiver of the information.

The drawing shows a block diagram of the proposed device.

The device for information exchange contains a receiving unit 1, a buffer register 2, a receiving and issuing control unit 3, an issuing unit 4, a trigger 5

mode, communication unit 6 with the channel, mode analysis unit 7, delivery counter 8, communication unit 9 with subscribers, load register 10, reception counter 11, Members 12-14, element 2I-OR-NOT 15,

an NOT element 16, a modulo-two control unit 17, a check bit generation unit 18, a check-bit conversion unit 19, a trigger 20.

The device works as follows.

In general, the data formats of the multiplex channel and subscribers can be arbitrary.

For information sharing unit

channel information (the syllable is assumed to be a seven-bit character (with the check bit is an eight-bit syllable, and the subscriber's information unit is a byte (with the check bit is the nine-bit syllable). Character conversion to bytes and vice versa is done through buffer register 2.

The device has two exchange modes: in the first exchange goes from the subscriber to the channel (Input mode), in the second exchange goes from the channel to the subscriber mode Output. When entered into the buffer 5, the register is filled with bytes, and characters are output from it, on the output - on the contrary. With each subscriber, the channel is exchanged successively in syllables, in one cycle, an array equal to one machine word (in this case, the length of the array is 32 bits, which corresponds to the common length of the machine word, and the word consists of four bytes or five characters, but the fifth least significant bit contains zeros.In the Input mode, the subscriber issues a request perceived by the communication unit with subscribers 9. When the connection is established, block 9 will block 7 in order to determine the exchange mode. poll result the mode trigger 5 is set to the state corresponding to the exchange mode of this subscriber. The byte with the console bit issued by the subscriber through node 1 enters block 17 and simultaneously the non-supervision byte is buffered into register 2. modulo two received bytes. In the case of the Normal control, the signal from the output of block 17 is not issued, and in the case of Reject control, the signal from the output of this block goes to the input of 1 flip-flop 20 and includes it in 1. Byte entry into the buffer register 2 control unit 3 and counter 11 admission. Block 3 generates a strobe that inserts a byte into the buffer register. The same strobe sets to 1 16 the first register trigger 10 load, after which counter 11 is transferred to state 1, this indicates that the first data byte is inserted into the buffer register. After the first byte has been entered, block 3 issues a signal to block 6, on which the last one issues a request, is a sign for the channel that the device is ready to read a character. At the same time, the check bit formation unit 18 produces the generated check bit of the symbol, which in the case of the input byte control norm passes without change through the block 19 and enters the output unit 4. When the channel reacts to the request, it sends to block 6 a signal to determine the mode of exchange with this subscriber. Block 6, according to the state of the mode analysis block 7, issues a flag recognizing the mode, and then a character coming from node 4. The issued character contains the seven most significant bits of the byte in the buffer register and the check bit. After the character is issued, counter 8 the output is translated to 1 and returns to its original state the trigger .20. In the case of a Reject control of the input byte, the generated check bit from the output of block 18 enters block 19, where it is converted to an inverse value (distorted and, similar to that described, is output in the character format (8th bit) to detect an error in the DVR reception Block 19 operates in accordance with the table.

 entrance entrance

ABOUT

G-1 entrance

II 1 ft input

About G-2 entrance

ABOUT

Claims (2)

1 „.,. Note For issuing a second character, the second byte from the subscriber who issued the first byte is required in the buffer register. Therefore, after receiving the first byte, block 9 does not interrupt communication with the subscriber. Block 9 blocks requests from other subscribers, and gives the subscriber the potential, which is for the subscriber a sign of readiness to receive next bytes from him (a sign of monopolistic exchange between the subscriber and the channel. Monopolistic exchange mode is kept until four bytes of data are received Reception of the second and subsequent bytes followed by receiving the first byte. After receiving the second byte, the second character is output to the channel, followed by the check bit and containing the remainder of the first byte and the higher bits. The second byte is written. At the same time the second character is issued, the load register trigger set in J when the first byte is entered in the buffer register is reset to 0. The output counter is set to state 2. The remaining three characters are issued in the same way. As the characters are issued, the register triggers are reset downloads set to 1 when storing these bytes in the buffer register. After issuing the last character, the issue counter is transferred to state 5. This is a sign of the end of communication with this subscriber. According to state 5, the delivery counter in the communication unit with subscribers is reset to the sign of monopolistic mode, i.e. The blocking of requests from all subscribers is removed. The initial state is driven by the units of the device for the exchange of information. In the output mode, the operation of the device is similar. The difference is as follows. (positive) signal level. Logic state 1 corresponds to a low negative signal level. After establishing the connection with the subscriber and determining the exchange mode, the communication block 6 with the channel issues a request to the channel. After the channel has received the request and polled the exchange mode, it enters the character in block 6, which is entered into the buffer register 2 In this case, a symbol with a check bit enters block 17. The insertion of a symbol, its modulo control and the formation of a check bit (byte) are accompanied by the same actions as in Input mode. After entering 2 characters in the buffer register 2, block 3 organizes the issuance of the first byte to the subscriber through block 9. Issuance of the following. Bytes to the subscriber becomes possible as the next characters from the channel are received. After receiving the dat symbol, block 6 stops issuing exchange requests to the channel. When the issuance of the fourth byte is completed, block 9 removes the indication of exclusive mode, as a result of which communication with the subscriber is terminated. Thus, the proposed device allows to increase the reliability of information during the exchange of multi-format data, since the device provides the exchange of multi-format data with control bits in syllables with simultaneous control of information modulo two. Claims 1. Device for the exchange of information on the author. No. 528561, in order to increase the reliability of the exchange, a block for forming a control bit, a control unit for two or more, and a block for converting a control bit, the first the control unit modulo two and the control bit formation block are connected to the first input and output of the buffer register respectively, the second inputs are connected to the mode trigger output, and the outputs to the first and second inputs of the control bit conversion block, the third input and output of the connected respectively, with the fourth and first inputs of the outgoing node. 2. The device according to claim 1, characterized in that the block of conversion of the control bit contains a trigger, single and zero inputs connected respectively to the first and third inputs of the block, and element 2I-OR-NOT, the first two inputs of which are connected respectively to the second input the block and the zero output of the trigger, the second two inputs with a single trigger output and through the element NOT with the second input of the block, and the output with the output of the block. Sources of information taken by BQ attention in the examination 1. USSR author's certificate №528561, cl. S 06 F 3/04, 1974 (prototype.