SU1487057A1 - Computer/external device interface - Google Patents

Description

FIELD: computing2.

technology, in particular, to devices for the exchange of information between the mainline computer and a group of external devices. The purpose of the invention is to increase the number of connected external devices. The device contains blocks of transceivers, blocks of receivers and transmitters, two address decoding blocks, two switches, an encoder, an address counter, two signal conditioners, AND, AND-OR elements,

2 hp ff, 4 ill.

The invention relates to computing, in particular to devices for the exchange of information between the mainline computer type "common bus" and a group of external devices.

The purpose of the invention is to expand the scope by increasing the number of connected external devices.

Figure 1 presents the block diagram of the device for pairing; FIG. 2circuit of the first signal conditioning unit; FIG. 3 is a diagram of the second signal conditioning unit; Fig, 4 scheme of the encoder.

The device contains blocks 1 and 2 transceivers, receiver unit 3, first address decryption unit 4, first switch 5, interrupt unit 6, second address decryption unit 7, memory unit 8, second switch 9, encoder 10, address counter 11, transmitter unit 12 , the second signal generation unit 13, the first signal generation unit 14, the second element AND 15, the third element AND-OR 16, the third 17 and fifth 18 AND elements, the first 19 and second 20 AND-OR elements, and the first 21, sixth 22 and the fourth 23 elements I.

The first signal conditioning unit 14 forms the element NOT 24, the register 25, the third 26, the first 27 and the second 28 elements AND, as well as the junction elements 29-33 (resistors).

The second signal generation unit 13 includes an HE element 34, the second element AND 35, a trigger 36, the third element I 37, the element I 38, the first element I 40 and the element 41 junction (resistor).

The encoder contains elements AND 42-46 and the element NOT 47,

Consider the operation of the device on the example of using a computer with a trunk parallel interface. When working with external devices (WU), the computer generates the address of the WU.

The upper and lower address bits come respectively to the first and

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1487057

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the second group of information inputs of the address decoding unit 4, the control sync signals are received from the mainline of the computer through the receiver unit 3 to the group of control inputs of the address decoding unit 4. The presence of the required address is fixed at the third output of block 4. Next, from the main line of the computer, read or write information signals are received through the group 3 mode identification input inputs, resulting in signals generated at the outputs of the AND-OR 16, AND 23 elements. The control signal c. the output element And 23 allows the passage of the younger part of the address from block 4 to block 12 transmitters and further to the main address of the slave. The computer, after the exchange of synchronization signals, transmits, via blocks 1 and .2 of transceivers, data arriving at the data line of the slave. .

The signals to write or read data for WU organize the second shaper 14 signals. In this case, the clock input of the imaging unit 14 receives sync pulses, according to which, if there is a permit, the recording and readout signals are generated at the third information input of the imaging unit 14 on the first and second outputs.

When WU is ready for information exchange with a computer, a signal is generated on the readiness bus of WU, the signal arrives at the second mode input of the second driver 13, the second output of the driver 13 is fed to the input of the AND-OR element 20, where together with the signal from the second decoder 7 address generates a control signal for the switch 9. The readiness signal from the switch 9 through the unit 1 transceivers enters the highway. The control signal for block 1 is generated by elements And 17 and 21. Switch 9 under the control of the encoder 10 transmits to block 1 data from the slave unit through block 2, the address of the interrupt vector, the address of the state register of the slave requiring interruption, from the counter 117

When working with the use of the interrupt mechanism, the enable bit of the interrupt is written to the memory block 8 by the addresses of the slave status registers. Recording is carried out under the control of the signal from the output element And 22.

In the absence of circulation from the main line of the computer device for interfacing

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15

20

25

thirty

35

40

45

50

55

autonomously polls the slave readiness, In this case, the sync pulses from the third output of block 13 are sent to counter 11, the outputs of which sequentially form addresses of the status registers of the slave through the switch 5 to the address inputs of memory block 8, while reading the contents of block 8 through each address through a block of 12 transmitters. If the desired slave is ready to exchange information, a “Ready” signal must be formed in it, therefore when accessing the corresponding WU, the “Ready” signal goes to the second mode input of block 13. The fourth mode input of block 13 from block 8 receives the interrupt enable bit read at the register address of the state of the slave. In the presence of these signals, block 13 stops the formation of clock pulses and the counter 11 stops at the address of the status register of the slave that is ready for operation ·. At the same time, from the first output of block 13, the signal is fed to the 'ready input of block 6 and to the input of the element AND-OR 20 "

Interrupt unit 6 generates an interchange exchange algorithm with a computer backbone, the interrupt vector code is generated from the output of switch 9 under control of the encoder 10. To determine the slave requiring interruption, there are two addresses of the status registers and data. Upon receipt of an interrupt vector, a computer handles a read operation in software. The address of the required data register is decrypted in the second block 7 of address decryption, and the signal is fed to the input of the encoder 10, in which the control code of the switch 9 is generated taking into account the operation of the block 4. The outputs of the switch 9 from the counter 11 of the address receive the address of the status register that stopped counter,

Ready VU can be determined by reading it, the ready bit goes to switch 9 from the output of the element AND-OR 20 in the presence of an enable signal from the output of block 7 and a ready signal at the second output of block 13,

Claims (3)

Claim 1, A device for interfacing a mainline computer with external devices, 1487057 containing two transceiver units, receiver unit, interrupt unit, first address decryption unit, the first group of information inputs of which and the group of gate inputs are connected respectively to the first and second groups of outputs of the receiver unit, the group of inputs of which is a group of device inputs for connecting to the mode identification bus group the main lines of the computer and the first group of information buses of the main line of the computer, the first and second outputs of the receiver unit are connected respectively to the installation input and the input is allowed I interrupt unit, a group of outputs of which is a group of outputs of a device for connecting to a computer trunk interrupt and synchronization buses, a group of inputs-outputs of a first transceiver unit is a group of inputs and outputs of a device for connecting to a second group of informational busses of a computer, the output group of a first transceiver unit is connected with the second group of information inputs of the first block of address decryption and with g, a group of information inputs of the second block of transceivers, a group of inputs and outputs k Expensive is a group of inputs and outputs of a device for connecting external devices to a group of information buses, the enable input of an interrupt unit is connected to the output of a corresponding discharge of a group of outputs of the first transceiver unit, in order to expand the scope by increasing the number of connected external devices , two signal conditioning units, two switches, an address counter, a transmitter block, a memory block, a second address decoding block, an encoder, and three I- elements are entered into the device OR, six elements AND, and the bit outputs of the address counter are connected to the first group of information inputs of the first and second switches, the group of outputs of the first address decryption unit is connected to the second group of information inputs of the first switch, the outputs of which are connected to the information inputs of the second address decryption block, transmitter block and the address inputs of the memory block, the outputs of the transmitter block are the outputs of the device for connection to the address buses of external devices, a group of outputs of the second block transceivers connected to the second group of information inputs of the second switch, the third group of information inputs of which are connected to the output group of the encoder, the first and second gate inputs of which are connected respectively to the first and second outputs of the first address decryption unit, the first output of the interrupt block and the third gate input of the encoder and with the first input of the first element And, the output of which is connected to the authorizing input of the first transceiver unit, the output of the second decryption unit address connected to the first inputs of the first and second AND-OR elements and the fourth gate input of the encoder, the first output of which is connected to the first input of the second AND-OR element and the second input of the first AND-OR element, the second output of the encoder is connected to the first input of the second element And, the output of which is connected to the block enable input, an interrupt, the second output of which is connected to the third input of the first AND-OR element, the output of the first AND-OR element is connected to the control input of the second switch, the output of the second AND-OR element is connected to Odom permit the second switch, the clock inputs of the first and second blocks. signal conditioning devices are input to a computer mainline bus, the first output of the receiver unit is connected to the installed inputs of the first and second signal conditioning units, the third output of the receiver unit is connected to the first input of the third AND-OR element, the first input of the third AND element and information input of the first signal conditioning unit, the first and second outputs of which are outputs of the device for connecting respectively to the write and read buses of external devices Tille output of the first signal generating unit connected to the input interrupt block mode input readiness is connected to the third input of second AND-OR and the first output of the second signal generating unit, the second output of which is connected 1487057 with the fourth input of the second element AND-OR, the fourth and fifth outputs of the first signal conditioning unit are connected respectively to the first input of the fourth element AND and to the first mode input of the second signal conditioning unit, the second mode input of which is the input of the device for connection to the readiness bus ^ external devices, the fourth output of the receiver unit is connected to the second information input of the first signal conditioning unit, the first inputs of the fifth and sixth And elements, the second 15 * input of the second And elements and The first input of the third element AND-OR, the output of which is connected to the third information input of the first signal conditioning unit, the third mode input of the second signal conditioning unit and the second input of the fourth element AND, the output of which is connected to the control input of the first switch, the sixth output of the first 25 signal conditioning unit connected to the third input of the second element And and the second input of the sixth element And, the output of which is connected to the recording input of the memory block, the information input of which is connected to the output of the corresponding The first and second outputs of the memory unit are connected to the fourth input of the first AND-OR element and the fourth ^ 5 clamping input of the second signal conditioning unit, the third output of which is connected to the counting input of the address counter, the second output group the switch is connected to a group of information inputs of the first transceiver unit, the output of the third element I is connected to the second input of the first element I, the third output of the first ^ address decryption unit is connected to the third and fourth inputs of third AND-OR, the second inputs of the third and fifth AND gates, the output of the fifth AND gate connected to the control input of the second transceiver unit. 2. The device according to claim 1, characterized in that the first signal generating unit contains the element NOT, a register, three elements And, and five elements of the junction, and the clock and. the third information inputs of the block are connected respectively with the first synchronous input and the first control input of the register, the installation input of the block is connected to the second synchronous input and the second control input of the register, the first and second information inputs of the block are connected respectively to the first inputs of the first and second elements, And the information inputs of the register of the block are combined and connected to the first output of the first junction element, the second terminal of which is connected to the zero bus, the output of the first element And is connected to the first terminals of the second and third elements of the junction and is the first output m block, the output of the second element And connected to the first conclusions of the fourth and fifth elements of the junction and is the second output of the block, the second conclusions of the second and fourth elements of the junction are connected to the zero bus, and the second conclusions of the third and fifth elements of the junction are connected to the positive power supply bus, the first the output of the register is connected to the input of the element HLO and is the fourth output of the block, the second output of the register is the fifth output of the block, the third output of the register is connected to the first input of the third element I and is third output block, the output element is coupled to the second input of the first AND gate and a second input of the third AND gate, whose output is connected to a second input of the second AND gate and a sixth output device. 3, The device according to claim 1, 1, and tl, which is due to the fact that the second signal conditioning unit contains three NOT elements, three AND elements, a trigger and a decoupling element, wherein the clock input of the block is connected to the input of the first element NOT and the first input of the first element And, the output of which is connected to the input of the second element NOT, the output of which is connected to the synchronous input of the trigger, the direct output of which is connected to the first input of the second element I, the output of which is the second output of the unit, the installation input of which is connected to the direct input of the trigger, information the input of which is connected to the output of the third element And, the first input of which is the fourth mode input of the block, in9 1487057 ten the trigger output is the third output of the block, the third mode input of which is connected to the second input · the primary element AND, the third input of which is the first mode input of the block, the output of the first element is NOT connected to the second input of the second element AND, the second mode the input of the block is connected to the first junction output and to the input of the third element NOT, the output of which is connected to the second input of the third element I and is the first output of the block, the second output of the isolation element is connected to the positive power supply bus, 1 1487057 Fig.Z 1487057 fi? .4-