SU822166A1 - Interface matching device - Google Patents

Description

one

The device relates to computing technology and can be used in control computing complexes, using a common bus interface and containing peripheral devices using other interfaces.

Interface devices are known that contain a descrambler, a control register, an interrupt execution unit, an exchange unit, a switch switch, amplification units, the first of which is connected to a common computer bus, and the second is connected to a common pin of the peripheral system.

These devices allow interfacing the peripheral line for connecting peripheral devices with a common computer bus 1

The disadvantage of these devices is low bandwidth due to the absence of the possibility of direct access of the computer program to any peripheral device without taking into account the occupancy of other devices connected to the same interface line. Also known. The device requires intermediate data buffering, and periphend commands,. 2

in the internal registry of the device. These drawbacks complicate the programs for peripheral devices and reduce the speed of the exchange with them.

The closest to the invention in its technical essence is a device for interfacing a peripheral system in a computer, comprising a de encryption unit, an exchange unit, a unit executed by-. neither interrupts, gain blocks, the first of which is connected to the common bus of the computing complex, the second to the peripheral device interface buses, the first input of the first gain block is connected to the output of the interrupt execution block, the first and second outputs of the first gain block are connected respectively to the first input the decoder and the first input of the interrupt execution unit; the first output of the exchange unit is connected to the first input of the decoder 2}.

However, this device is characterized by a low bandwidth, as it does not provide for independent software access to peripheral devices of an interface connected to a common bus, the same as peripheral devices connected directly to a common bus. Software access to the peripheral devices of the interfaced π interface is carried out through a group device having its own addressable control register and the initiating and reading scheme of the interrogation request word. The presence of a group device significantly complicates the program call to peripheral devices connected through it, especially in the case of a multiprogramming mode of operation of the computer complex, since it additionally requires a series of program actions to eliminate the possibility of conflict situations when servicing the connected devices. It complicates the programs in this device also that the response signals (indications of the result of the operation from various peripheral devices and registers) are read out by the program t; one common register and that enable-disable interrupt is set simultaneously on all peripheral devices. In addition, work with peripheral devices is carried out only using interrupts.

The purpose of the invention is to increase the capacity of the device, as well as expand its functionality to simplify computer software and increase

management flexibility.

1- The goal is achieved by the fact that in the device containing the gain blocks of the first and second interfaces, the inputs-outputs of which are the corresponding inputs-outputs of the device, the interrupt block

respectively, connected by the first input and output with the first output and input of the gain unit of the first interface, the second input and output of which are connected respectively to the first output and input of the exchange unit, the third input to the switch output, and the third, fourth, fifth and sixth outputs to the first input of the control unit of the control signals, the input of the selector and the first inputs of the decoder and the receiving register danHbix, the second input connected to the second output of the block exchange, the third, fourth outputs and the second input of the second connection each with the first input of the switch, the second input of the control output unit and the output of the selector, and the fifth output of the exchange unit to the second input of the decoder, the first output connected to the first input of the second interface gain unit, the second and third inputs of which are connected respectively to the output the control signal output unit and the first output of the receiving data register, and the first

output - to the second input of the switch; a priority block, an encoder and a block of command registers are entered, and the first and second outputs of the block of command and status registers are connected respectively to the first input of the priority block and the third input of the switch, the first and second inputs are respectively to the second outputs the decoder and the receive data register, and the third input - with the second inputs of the gain block of the second interface and the priority block, the first output connected to the second, input of the interrupt block, and the second output - through the encoder to the fourth input of the switch.

The drawing shows the block diagram of the device.

The device contains a decoder 1 intended for generating signals of a sampling of devices connected to the second interface and their registers of commands and states, an exchange unit 2 executing the procedures provided for by the algorithm of the first interface; block 3. interruptions; implementing the operation of interrupting a computer program; a gain unit 4 of the first interface, a gain unit 5 of the second interface, a receive data register 6 that receives and transmits data of the first interface to the data lines of the second interface or the corresponding command register of states; switch 7 ,. carrying out the output to the data bus of the first interface information from the second interface bus, the encoder and from the command and status registers; the selector 8, which identifies the addresses assigned to the devices of the second interface to the address of the first interface, and enables the operation of the exchange unit; block 9 provides control of the bad signals, designed to form from the operation codes and lower addresses of the first interface the corresponding control signals of the second interface; block 10 of registers of commands and states containing one register for each device connected to the second interface, an encoder 11 that converts the number of the selected device, the computer program interrupt vector; block 12 priorities, which ensures the selection of the highest priority service request from all requests received from devices connected to the second interface.

The first interface is a unified backbone communications system between the processor, the operating system and the peripheral devices. Communication between devices involved in the operation.

exchange, carried out in an asynchronous manner.

The second interface is a unified trunk communication system for data and control signals and radial communications for device sampling signals and availability indications. The connection between the central and peripheral parts of the interface is controlled by the central part.

Each device connected to the second interface corresponds to two addresses on the address buses of the first interface: the address of the command and status register and the data register address. The device exchanges data between the computer using the first interface and devices connected to the second interface, both in the program exchange mode and in the interrupt mode.

In the program exchange mode, the device operates as follows.

As a rule, before accessing an external device, the device is ready for interrogation using the read command command of the corresponding register in block 10 of the command and status registers. For this purpose, the computer, via amplifiers 4 of the first interface, provides the address of the register of commands and states of the required device connected to the second interface. The decoder 1 generates from the received address the sampling signal arriving at unit 10.

At the same time, the selector in determines whether the address issued on the first interface belongs to a range of device addresses; connected to the second interface, and start up the exchange unit 2, which reads the selected register of commands and states in the computer, through the switch 7 and the amplifiers 4 of the first interface, and the state of the discharge corresponding to the readiness of the device is read directly from the radial readiness bus specified device. If the readiness bit is in 1, then the computer proceeds to perform an information exchange operation with the corresponding device connected to the second interface, if the readiness bit is in O, then the computer repeats the reading operation of this register of commands and status down to 1. in de readiness. When reading the command and status registers, no control signals are output to the second interface.

Issuing or receiving information from the; Device connected to the second interface is carried out by one computer command connected to the first interface.

When the information is entered, the address of the device connected to the second interface goes to the selector 8, the decoder 1 and the control signal output unit 9, the data through the amplifiers 4 of the first interface to the input of the data register 6 and the write operation code to unit 9 and unit 2 exchange.

The signal selector 8 unit 2 exchange puts the data code in the receiving register 6 and starts the decoder 1 and block 9. The data from the receiving register 6 through the amplifiers 5 are received on the data line of the second interface. The decoder 1 outputs to the second interface a signal from the device sampling corresponding to the received address. According to the operation code and the state of the lower bits of the address, block 9 forms a sequence

0 signals, which are recorded in the device, for which there is a sampling signal, data received from the computer, and also performs other actions in the device, provided by the second interface's algorithms

5 and this device.

Receiving information from a device connected to the second interface is different from sending information to the device in that block 9 and block

0 2 exchange receives the read operation code, according to which, the control signal issuing unit 9 generates, taking into account the state of the lower address bits, the signals on which the information from.

5 of the device, for which there is a sampling signal, via data lines through amplifiers 5, switch 7 and amplifiers 4 enters a computer. The exchange of the necessary synchronization signals on the first interface in the process of receiving or issuing information is carried out by exchange units 2.

Thus, in the program exchange mode, each cycle of the second interface exchange is initiated by one

5 cycle exchange of the first interface. This allows one computer command connected to the first interface to perform all the necessary actions on data exchange with the device connected to the second interface, as well as the computer program, using the first interface, to access the devices connected via the second interface. how: to

5. devices connected to the first interface, without additional software actions for the coordination of interfaces.

In interrupt mode, the device operates as follows.

0

On commands from a computer, registers of commands and states related to external devices, which are allowed to work in the interrupt mode, are recorded 1 time 5

interrupt solutions. The outputs of the interrupt enable bits go to priority block 12, where they allow readiness signals from the corresponding external devices to participate in prioritizing the call to the computer program interrupt on these signals, and also on signals

OSH1 | 6OK. ,

Out of all simultaneously received signals from external devices, priority node 12 identifies the most priority signal, taking into account the presence of interrupt permissions for each device connected to the second interface. The selected signal enters the encoder; 11, which converts the signal received at its output and the interrupt vector of the device, and to the input of the interrupt block 3, which carries out the exchange of the necessary clock signals provided by the algorithm of the first interface. . In particular, this algorithm provides for the transfer to the computer over the data buses of the gdaerve vector arriving from the encoder 11 through the switch 7. The interruption of the interrupt routine ends with the transfer of the vector interrupt computer. Then the computer proceeds to the execution of the service program of this interruption.

Thus, in the interrupt mode, as well as in the program mode, it is possible for the program to perceive the devices of the second interface as connected directly to the interface for the interface and to take full advantage of all the architectural capabilities of the common bus. This allows you to shorten the device maintenance programs J connected to the second interface, reduce their execution time and, consequently, increase the speed of information exchange with these devices and reduce the response time to interrupt signals from them.

The use of the proposed device for connecting to a computer, using the common bus interface, the devices exiting the main radial interface, makes it possible to reduce the I / O programs and their execution time during the program exchange and Four times and more, reduce the response time of a computer to interrupt requests when working with interruptions. . The device is used in a common tire and a 2K type matching device (USS OSH / 2K), used in accordance with the ESS, SM4 and CM1 and CM2 models included in the small computer system (SM computer).

The USS OSH / 2K device allows using the entire nomenclature of peripheral devices of the CM1 and CM2 models in the SMZ and CM4 models, and the programming for these devices connected to the SMZ and CM4 via USSSOS / 2K is similar to programming for devices connected to the SMSW and. CM4 directly through the common bus.

Claims (2)

Invention Formula A device for matching the interfaces, containing the gain blocks of the first and second interfaces whose inputs are the corresponding inputs / outputs of the device, an interrupt block connected to the first input and output respectively to the first output and input of the gain block of the first interface, the second input and output KQToporo are connected respectively to the first output and input of the exchange unit, the third input to the output of the switch, and the third, fourth, fifth and sixth outputs, respectively, to the first input of the control unit, the selector input and the first input of the decoder and the receiving data register, the second input of the exchange unit connected to the second output, the third, fourth outputs and the second input of which are connected respectively to the first input of the switch, the second input of the control signal unit and the output.selector, and the fifth, output of the exchange unit - to the second input of the decoder, the first output of the second interface connected to the first input of the gain unit, the second and third inputs of which are connected respectively to the output of the control signal block and the first output of the receiving data register, and the first output - to the second input of the switch, characterized in that, in order to increase the capacity of the device, a priority block, a coder and a register of commands and status registers are entered into it, the first and second outputs the block of command and status registers are connected respectively to the first input of the priority block and the third input of the switch, the first and second inputs to the second outputs of the decoder and the receiving data register, respectively, and the third input to the second inputs of the block power of the second interface and the priority block, the first output of the interrupt block connected to the second input and the second output through the encoder to the fourth input of the switch. Sources of information taken into account in the examination .1. US Patent No. 3714635, cl. 340-172.5, Publication 1973. 2. USSR author's certificate 554534, cl. G 06 F 3/04, 1975 (prototype).