SU1408440A1 - Interface of computer with peripherals trunk line - Google Patents

Description

not with computer trunk information buses, first, second and third inputs and output, respectively, with the output of the first address decryption block, the output of the capture signal of the highway capture block, with the output and input of the interrupt block interrupt, and the fourth input with the trunk stop request buses external devices.

2. The device according to claim 1, characterized in that the request processing unit of the passive devices contains a priority node, a clock input connected to the output of the clock generator, two elements AND, input and output switches and element NOT, the output of the first element AND connected to the control input of the input switch and through the element NOT with the input of the permission to write the code of the current priority of the node

08440

priority, the input of the current priority code of which is connected to the output of the input switch, the control input of the output switch is connected to the output of the second And element, the information inputs of the output switch are connected to the output of the priority node priority vector and the third input of the passive devices request processing block, the first and second inputs of the second element And connected to the third input of the request processing unit of passive devices, the output of the output switch is connected to the information input of the input switch and in The one output of the passive device request processing unit, the input and input group of the first element AND, the group of request inputs and the output of the priority node interrupt request signal are the second, first and fourth inputs and output of the passive device request processing unit, respectively.

one

The invention relates to computing; technology and can be used to interface computing systems that have an interface like a common bus (OSH) with computing systems that have an interface like a trunk and are included in a hierarchical structure.

The purpose of the invention is to reduce the time for establishing a connection between a computer and an external device.

Figure 1 presents the block diagram of the device; Figures 2-6 are functional diagrams of a control unit, a unit; interrupts, line capture block, buffer data register, and passive device request processing block, respectively.

The device (Fig. 1) contains the first address decoding unit 1, the interrupt block 2, the preregional register 3, the buffer register 4, the address register 5, the command register 6, the processing unit 7, the request for the passive device, the control unit 8, the second address decoding unit 9, block 10 capture ma

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gistral, first information input-output 11, address input 12, first control input-output 13, second information input-output 14, address input-output 15, interrupt request input 16, second control input-output 17, request output 18 access to the trunk, input 19 destroys access to the trunk of the device and bus 20-23 of the internal communications of the device.

Inputs-outputs 11 and 13 and input 12 are connected to information, control, and address bus lines of the computer main, inputs-outputs 14, 15, and 17, inputs 16 and 19, and output 18 to the corresponding bus lines of external devices.

The control block 9 (FIG. 2) contains a clock pulse generator 24, shifting the registers 25 and 26, the second, fourth, third and first triggers 27-30, the second, third, fourth and first elements AND-31-34, ele- .ment I 35, shaper 36 pulses and decoder 37.

Interrupt unit 2 (FIG. 3) contains the first third and second triggers 38-40, NPI elements 41 and 42, the second, first and third elements AND 43-45, AND-NOT elements 46 and 47, HE element 48.

Block 10 capture line (figure 4) contains the trigger 49, the elements And 50 and 51 and the switches 52 and 53,

Buffer register 4 data (figure 5) contains the elements And 54 and 55. pue 56 and second 57 switches, consisting of groups of three-stable elements And ..

The request processing block 7 of the passive devices (FIG. 6) contains the output switch 58, the priori, theta node 59, the second element 60, the input switch 61, the first element 62, the element 63 and the generator 64 clock pulses

The device operates as follows: The data exchange between the OSH processor and the interface of the trunk is performed by restoring the logical connection of the OSH processor to the

at once.

The processor OT exposes a line to the input 1225 via a buffer address A18-AO, in which bits A18 are register 4. A3 define basic devices, A2 - calls to internal registers of the device or data exchange, A1, AO - internal register codej input / output 11 sets the data when

In the data management unit of the data exchange processor, the IO processor sends into the register 5 the addresses of the interface device 30, which is being accessed, and in register 6, the control command that determines which device is exchanged (the input-output device or the storage device). (Memory) information output, and the input-output 13 - the signal Yi, defining with a logical unit Input, and with zero Output, accompanying the indicated signals with the signal СХЗ (sensor synchronization) at the input-output 13,

Block 1, using the signals of А18-АЗ, forms the signal of Sample 1, which determines the access to the device. In addition, the Q-queue Trunk is executed next, block 1, by a combination of signals from CX3, Y1, A2, A1 and AO, generates a control signal for registers 4-6 and block 7, providing writing or reading information from input-output 11 to the specified devices, and also the data exchange between the inputs-outputs 11 and 14. In case of the OSH processor registers 4-6 and block 7, the execution of the I / O operation is determined by the time of their operation and therefore the generation of the SHI signal (synchronization of the performer), which is a communication signal that the device is manufactured lo action input-output operations, is performed in block 8 to SKHZ signal with a delay time defined by a tripping registers.

sequence of actions: seizing the highway, i.e., sending the access request signal to the highway 18 (MMD) and receiving, according to a du 19, the signal of accessing the highway (RDM), outputting the device address to the input-output 15, transferring to the input- the output 17 of the corresponding control signal (write, read,

cQ issue, receive) and wait for the exchange with the addressable device, i.e. receiving on the input-output 17, the signal Answer.

To exchange the processor, the OI exposes to the input 12 the address of the device with the indication of the exchange via the interface Highway, accompanying it on the input-output 13 with the signal of the APS, and exposes to the input-output 13 the signal

55

The operation of block 8 is as follows (figure 2). The CXP signals from I / O 13 and Sample 1 from block 1 through bus 21 are fed to the inputs of element I35, the output of which trigger 30 is set to the state corresponding to the value of signal U1, and trigger 27 to one. A logical zero appears at the output of the NAND 32 element, since its inputs receive single signals from the trigger 27 and the A2 signal via the bus 21. The logical zero from the output of the NAND 32 element goes to the AND-NE element 33, which forms at its output logical unit. A signal of SCI. At this point, the cycle of accessing the OSH processor to the device is completed.

Data exchange between the OSH processor and the interface of the trunk is accomplished by restoring the logical connection of the processor of the OR to the interface of the trunk through the buffer register 4.

Dp of data exchange device operation control, the processor OI sends to the register 5 the addresses of the interface device, the trunk to which the call is made, and to register 6 a control command that determines which device is exchanged - the input device or the storage device (memory )

and interface capture mode Trunk (permanently (request) or the time it takes to transfer a single word, etc.). To perform an exchange on the Trunk interface, the following sequence of actions is performed: trunk capture, i.e., sending the access request signal to output 18 (MMD) and receiving on input 19 of the signal of access to the trunk (RDM), outputting the device address to input-output 15, and transmitting to the input-output 17 of the corresponding control signal (write, read,

issuing, receiving) and waiting for the exchange with the addressed device, i.e. receiving on the input-output 17, the signal Answer.

To exchange the processor, the OI exposes to the input 12 the address of the device with the indication of the exchange via the interface Highway, accompanying it on the input-output 13 with the signal of the APS, and exposes to the input-output 13 the signal

Yl. In the case of an output from the interface, the OR data is output to input-output 11. When the CXS signal arrives, unit 1 generates an exchange signal and a B1 signal that determines the direction of the exchange, the download of which, when outputting data, is equal to logical one, and when entering, logical zero. Sipgal Exchange via bus 21 enters block 10 and sets trigger 49 to the zero state. The logical zero from the output of the trigger A9 goes to the element I 50 and from its output through the switch 52 enters the output 18 as an EDM signal. The signal of the RDK, represented by a logical unit at input 19, through the switch 53 enters the direct input of the element 51, to the inverse input which receives a pin signal from the output of the element And 50. As a result, at the output of the element And 51 there is a logical unit, which is a sensing signal

The Capture signal through the output of block 10 via bus 22 enters the inputs of buffer register A, register 5 and. Blocks 7 and 8. On this signal, register 5 gives the address to .1 output-output 15, buffer register A passes: data from the input- output 11 to input-output 1A, if there is a B1 signal at its input equal to a logical one, and vice versa — if there is a signal at this input B1 equal to logical zero, it provides data transfer from input-output 1A to input-output 11. The opening of the corresponding switches 56 and 57 provide elements AND 5A (transmission from input 11 to input-you ode 1A) and AND 55 (transmission from the input-output 1A of the input-output 11)

In block 8, the Capture signal through the information input of register 25 is advanced to its outputs by generator 24; then from the first one goes to the information input of the shift register 26, and from the second to the synchronization input of the trigger 29,

its transfer to the zero state. The signal from the output of the trigger 29 is fed to the first input of the decoder 37. At this time, the remaining inputs of the trigger / charger signals, Sample 1 and YI are present. The decoder 37 for the combination of input signals generates signals Record or Read, if the exchange occurs with the memory, or signals Receive or Issue, if

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the exchange takes place with an I / O device, and gives off nx to input / output 17. The device with which the exchange is carried out by executing onepauiflo exchange triggers the control signal. The response, represented by a logic zero, which from input / output 17 goes to the information input of the shifting The register 26 and under the action of pulses from the generator 2A appears on its first, second and third outputs with a delay of one, two and three cycles, respectively. The signal from the first output of register 26 sets trigger 29 to one state, and trigger 28 to zero. In this case, the logical unit from the output of the trigger 29 blocks the operation of the decoder 37, and the logical zero from the output of the trigger 28 sets the logical unit at the output of the AND-NE element 33, which through the input-output 13 goes to the OSH processor as an SHI signal, which indicates that the exchange with the addressed device is complete. On this signal, the OR processor removes data from I / O 11, the address from I / O 12, and control signals from I / O 13. Deleting the CX3 signal causes the trigger 27 to go to zero, trigger 28 - in the unit. In this case, a logical zero appears at the output of the NAND 33, which corresponds to the removal of the control signal SHI,

The signal of the logical unit from the second output of the register 26 is fed to the first input of the AND-31 element, to the second input of which from register 6, via a bar 20, a signal is received. KIM zero. When an Incurrent signal is present by a logical unit, an address increment signal is generated at the output of the NE-31 element. The address increment signal is generated from the output of block 8 via bus 23 to the input of register 5 of the address and increases its content by one.

The signal from the third output of register 26 goes to block 10 and is the executive command Reset line capture. On this signal, trigger A9 is set to one, and a logical one appears at the output of AND 50, resulting in

Element And 51 appears logical zero, which captures the signals Capture and ZDM. After that, the buffer register A and register 5 are disconnected from the interface of the trunk and the RDM signal is removed. This completes the word exchange procedure.

In the case of the exchange of arrays from register 6 via bus 20 to the input of block 10, a request constant command can be transmitted by logical zero, which through the elements 50 and switch 52 provides a permanent capture of the interface trunk. In this case, the capture signal is permanently present on the bus 22 from the output of block 10, and therefore block 8 is started to exchange with the interface. The trunk is produced by the exchange signal, which through the AND-NO FOR element in the presence of a signal the capture sets trigger 29 to the zero position on the installation input.

When requesting communication from the bottom of the rus or the local subsystem, the request is made by the active element. In this case, the active element performs calls on the input-output 15 of the device. The address signal from input-output 15 is fed to the input of block 9, where it is decoded and when it is inputted at its other input

control signal Issue, post. scrap Vector interrupt I block 2

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; the flayer from input-output T7, block 9 forms the vector of pre-argoan and the signal of Sample II. The interrupt vector from the output of block 9 is fed to the input of register 3 and is fixed in it. The Sample II signal from the output of block 9 is fed to the input of block 2 interrupts and from it to the unit installation trigger 38. At the output of trigger 38 there is a logical unit, which is the g interrupt request signal, which through the elements OR 41 and AND 43 zero on the inverse of the last input goes to input-output 13, In response, the OSH processor issues an input-output 13 signal Interrupt enable — a logical unit that arrives at the inverse input of the And 45 element, after which the logical unit at its output changes to zero that fits Signal request interrupt. At the same time, the Enable Interrupt signal is supplied to the trigger input of the trigger 39, and

by means of the element NOT 48, a signal is received which is received from input-output 13 and indicates that the device has occupied the OSH interface.

In the processing program, the OS processor is interrupted. The Interrupt Reset command is written to the register, llo is issued to the command from the register 6 output. The reset via bus 20 is sent to the synchronization input of the trigger 38, zero setup input, trigger 40, set block 2 to its original position.

In the interface of the trunk for realizing communication requests (RAD), there is a radial trunk. In the case of a communication request for an exchange from the passive elements with the coordinator of the corresponding radial, the radial causes the processor to interrupt. At the same time, the active interface cop of the trunk does not respond to this request.

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since its information input already contains a logical unit from the output of the NE-47 element, it is transferred to the one state and the signal from its output goes to the information input of the trigger 40 and to the input of the And 45 element.

At the moment when the control signals of the SHI and Zahn at the inputs of the element OR 42 correspond to logical zeroes, the logical unit from the output of the element IS-NOT 46 arrives at the synchronizing input of the trigger 40 and translates it into a single state. The unit from the trigger output 40 is the UIP signal (sample confirmation), through the input-output of block 2, to input-output 13 and to the input of element I 45, at the other input of which there is already a unit from the output of trigger 39. At the output of element And 45 a logical unit appears, which is the signal of Interrupt Vector I, at which time the Interrupt Vector signal 20

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Nor II, formed by the element And 44, is equal to logical zero. These signals from the output of block 2 interrupts are sent to the register 3 interrupts and allow the output of its contents to input-output 11, causing the interrupting program.

Simultaneously with the control signal 0

by means of the element NOT 48, it forms the signal Zan, which is fed to the input-output 13 and indicates that the device occupied the OR interface.

In the interrupt handling program, the OSH processor writes to the register 6. a command to reset the interrupt, llo to this command from the output of register 6, a signal is reset via bus 20 to the trigger input 38 t, zero set input of trigger 40, set block 2 to the initial position.

There is a radial trunk in the interface of the trunk for carrying out communication requests (PDR). In the case of a communication request for exchange from passive elements with the coordinator of the corresponding. vukntsa radial causes an interrupt processor OSH. In this case, the active interface element Trunk does not respond to this request.

The DPR signal from an interrupt from input 16 is fed to the input of block 7 and then to the inputs of the preSignal Interrupt Vector II, together with the Interrupt I vector, switch 58 is opened,

the snatching of the node 59, which by providing 5 with this, to the input-output 11 is transmitted the arbitration vec- tion of the simultaneously received interrupts. Interrupt vector shaping depending on level, signal shaping

interrupt torus, which contains information about the level at which the interrupt is received (interrupt code from node 59) and that the interrupt is

provided that the level of at least one of the passive device (the added signal of the DPR is higher than the current highest-priority signal received by the senior vector of the rhythm recorded in node 59 of processing II). Record current OSH processor. Signal Pre-priority request to node 59 is carried out by the output of block 7, via an OSH processor from input-output 11, the third input of block 2, where through 15 switch 61, which OR 41 opens the formation of a signal in the same way as in the pre-input of the element AND 62. Inverting from the active device, and the nanny signal from the output of the element AND 62 from the output of the element AND 44 forms a signal for the recording circuit of node 59. General Interrupt Vector II, if the pre-20tor 64 clock pulses secured e reflected from the active device Vaeth-functioning node 59 to bot regimes and trigger 38 is in a well-me continuous analysis queries the left state, the interrupt.

The interrupt vector signal II, together with the interrupt vector signal I, opens the switch 58, with

this to the input-output 11 is transmitted

this to the input-output 11 is transmitted

interrupt torus, which contains information about the level at which the interrupt is received (interrupt code from node 59) and that the interrupt is

from a passive device (the high-order added signal is Interrupt Vector II). The current priority in node 59 is recorded by the processor OR from input-output 11 via switch 61, which open when the signals at the input of the element 62 coincide. The inverted signal from the output of the element 62 opens the recording circuit of the node 59 64 clock pulse generator ensures the operation of node 59 in the continuous analysis mode of interrupt requests.

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Claims (2)

1. A DEVICE FOR COMMUNICATING A COMPUTER WITH AN EXTERNAL DEVICE HIGHWAYS, containing the first address decryption unit, the first input of which is connected to the address buses of the main computer, the second input - to the control buses of the main computer, with the address inputs and outputs of the interrupt unit and the control unit, and the output - with the first synchronizing input of the buffer register of data and the first synchronizing input-output of the control unit, the synchronizing inputs of the command register and the capture block of the highway and the first information input of the address register, first the information input-output of the buffer data register, the second information input of the address register, the information input of the command register and the output of the interrupt register are connected to the information buses of the main computer, the output of the command register is connected to the information input of the data buffer register, command inputs of the control unit and the capture unit Master's. whether by the reset input of the interrupt block, the second information input-output of the buffer data register is connected to the information buses of the trunk of external devices, the output of the address register is connected to the address buses of the bus of external devices and to the first input of the second address decryption block, the second input of which is connected to the control bus lines external devices and with a second synchronizing input-output of the control unit, the first output of which is connected to the third input reset signal capture block capture line the solution and the input of the request of which q are connected respectively to the input and output buses of the access request of the trunk of external devices, the output of the capture signal of the capture block of the trunk is connected to the second clock input of the buffer register of data, the synchronization input of the address register and the input of the capture signal of the trunk of the control unit, the second output which is connected to the clock input of the address register, the first and second outputs of the second address decryption unit are connected respectively to the information input of the interrupt register and an enable input for the interrupt unit, the output of which is connected to the synchronizing input of the interrupt register, characterized in that, in order to reduce the time to establish a connection between the computer and the external device, a request processing unit for passive devices is introduced into the device, and the input-output of the request processing unit for passive devices connected to 1408440 A1 with information buses of the main computer, the first, second and third inputs and outputs, respectively, with the output of the first address decryption unit, the output of the capture signal of the capture unit of the mag and with the output and input of the interrupt request for the interrupt unit, and the fourth input ‘with the interrupt request buses of the trunk of external devices. 2. The device according to claim 1, characterized in that the passive device request processing unit comprises a priority node, a clock input connected to the output of the clock generator, two AND elements, input and output switches and an element NOT, wherein the output of the first element AND is connected to the control the input of the input switch and through the element NOT with the input permission to write the code of the current priority of the priority node, the input of the code of the current priority of which is connected to the output of the input switch, the control input of the output switch connected to the output of the second element And, the information inputs of the output switch are connected to the output of the priority vector of the priority node and the third input of the request processing unit of the passive devices, the first and second inputs of the second element And are connected to the third input of the request processing unit of the passive devices, the output of the output switch is connected to the information the input of the input switch and the input of the output of the request processing unit of the passive devices, the input and input group of the first element AND, the group of request inputs and output signal and interruption requests of the priority node are, respectively, the second, first and fourth inputs and outputs of the request processing unit of the passive devices.