SU596938A1 - System for interfacing terminal devices with computer - Google Patents

Description

The invention relates to the field of computing technology and can be used in the design of computers and systems.

A known system is capable of receiving and transmitting data from terminal devices to a processor. It contains a delay magnetostrictive line, a base register, a base register control device, a shift register and a shift register control device, and receives information transmitted in serial code (bit-wise) from a low-speed peripheral device. Peripheral data is poured through the shift and base registers into the delay line. Data output. The processor conducts through the shift and base registers with a parallel code of 8 bits initiated by n under the control of the processor. The system also provides for reverse data transfer. In this case, data from the processor is received in a parallel code, written to the delay line, and output to the peripheral device in a serial code.

The disadvantages of this system are that it does not have the ability to connect several terminal

devices; information is exchanged with the terminal device only in sequential code, which peSKo limits the variety of devices connected; the reliability of the information is low, both at reception and at the time of data output; only gave information to the processor in parallel code. Which excludes the possibility of connecting a modem for transmitting information over standard telephone channels to a remote processor; information is output to the processor by requests and by the floor of the control of the processor itself, which requires specialization of the processor and additional time costs; there is no possibility of primary data processing.

The closest in technical essence to the invention is a system containing an arithmetic-logical unit, a block of operational registers, a random access memory, a microinstructions register, a persistent storage, an instruction address counter, the first output of which is connected to the input of a permanent storage whose output is connected to the first input of the register of micro-commands, the second input of which is connected to the first output of the operational memory, the first output of the register of micro-commands is connected to The first input of the command address counter, the second output of the random access memory is connected to the first input of the operating registers block, the first output of which is connected to the first input of the random access memory, and the second output is connected to the first input of the arithmetic logic unit, the output of which is connected to the second input of the operating room registers, the second output of the instruction address counter is connected to the third input of the block of operational registers. This system receives information from a number of different types Terminal devices that receive and transmit information both in parallel code (edited typewriters, display devices, etc.) and in sequential code (teletypes, etc.) with different character width. The number of terminal devices to be connected can be varied and determined by the fact that the total input stream and 1 formation from the terminal devices should not exceed the capacity of the communication kit with the machine. The symbol formed by the terminal, the device is controlled at reception, and then an interference-proof packet of information to be transmitted to the machine is formed from the received symbols. The transfer of the generated information packet to the machine can be implemented both in parallel and in sequential code, depending on the mode of operation of the system. In addition, the system carries out the transfer of information from the machine to the terminal devices. HJHI, this information processing procedure involves receiving a jamming information packet from a machine, nposeipKy it and issuing it to terminal devices. With information on the connection channel, the system has the ability to re-request the received information package from the machine, if the latter was found to be distorted, and also to repeat the transmitted information packet to the machine on the program. In addition to these possibilities, the System allows the exchange of information with another interface system of terminal devices, without the need for aoggelic hardware costs. The disadvantages of the above system for interfacing the terminal devices with the computer are: the system does not have the capability of initial information processing; there is no possibility to transfer information between terminal devices connected to the system; There is no possibility of priority service of the connected terminal devices. The purpose of the present invention is to improve the efficiency of the system by providing primary processing of T1 information, transferring between terminal devices connected to the system, realizing the possibility of priority service of the connected terminal devices; The set of objectives is achieved by introducing a microprogram control unit, an analysis unit and a connection with terminal devices, connected to the terminal devices, a program tuning block, a priority processing block, the first output of which is connected to the interface for connecting the terminal devices with the computing machine. the first input of the micropOf unit poq) 3MMHoro control, the first output of which is connected to the second input of the address counter, the second output - to the second input of the arithmetic logic unit, t This output is the fourth input of the operating registers block, the fourth output is connected to the second input of the operational storage device, the second input of the microprogram control unit is connected to the second output of the micro-commands perHcipa, the second output of the priority processing initiation block is connected to the third input of the command address counter, the fourth the input of which is connected to the first input of the analysis and communication unit with the Terminal devices, the second output of which is connected to the first input of the block for initiating processing, sec The first input of which is connected to the first output of the program setting block, the second output of which is connected to the first input of the analysis and communication unit with terminal devices, the third output of which is connected to the fifth input of the operating registers block, the third output which is connected to the second input of the block analysis and communication with terminal devices, the third output of the priority processing initiation block is connected to the sixth input of the operating registers block, the fourth output of which is connected to the input of the program tuning block, third output software tuner soed1y1ei a seventh input of the operation: the registers. The drawing shows the structure of the system | w coiftp of female terminal devices with a computer. It consists of arithmetic; : a logical-logical device 1 for information processing, a block of 2 operational registers providing storage, addressing and internal links of the processed information during processing; a random access memory 3, which stores the information received from the terminal devices and is to be output to the computer, as well as the storage of information arrays, the received computer, and the data to be output; microinstructions register 4 for storing a microcommand at the time of its execution; a persistent storage ycTpjucTBa 5 for storing microinstructions defining an information processing rhythm; the address of the command address 6, which, in accordance with the input signals, generates the address of a microcommand that is read from the permanent storage device; microprogram control unit 7, which, in accordance with the micro-command code read into the micro-command register, generates control signals by the system unit to implement one of the actions in the information processing; block 8 priority processing initiation, ensuring the organization of priority service of terminal devices; a software setting unit 9 that controls the priority level between terminal devices; an analysis and communication unit 10 with terminal devices exchanging information with terminal devices and analyzing the signals received from them using exchange code machines; U terminal devices connected to the system ..

The main functional connections of the device are formed with the help of women; priority processing initiation 12; control counter address commands 13; control of the arithmetic unit 14; code register microinstructions 15; controlling the operating register block 16; managing the operational storage device 17; code records of operating registers 18; the code entries of the random access memory 19, the code readings of the random access memory in the register of microinstructions 20; code reads of operation registers 21; code reads of the random access memory 22; code records of the counter address commands 23; read-only code reads 24; code counter address commands 25; code block priority processing initiation 26; code block of program setting 27; code reads of program setting block 28; code readings of the analysis and communication unit with terminal devices 29; code records of the analysis unit with communication with the terminal devices 30; forming the initial address of the priority Processing 31; the control signals of the software setup block 32; clocking signals 33; generating processing address 34; controlling the priority processing initiation unit 35; code reads of the instruction address counter into the operational register block 36; code terminal devices 37..

The system receives information from a number of different types of terminal -... devices that receive and transmit information: ations both in parallel and in a sequential code with different symbol widths. The number of terminal devices connected to the System can be changed and determined by the fact that the total input information flow from the terminal devices should not exceed the channel capacity. The symbol constructed by the terminal device is controlled at reception, and then a noise-free information packet is formed to be transmitted to the mashine.

In the process of receiving and forming a noise-proof information packet, primary information processing is performed, which translates the received information from different types of terminals into a standard exchange code, identifies signs of beginning and end of the entered document, logically controls the document format, sifting out redundant information, etc. The level and content of the primary information processing can be arbitrary and determined by the necessary processing procedures for each specific go application.

The transfer of the generated packet of information to the machine can be carried out both in parallel and in sequential code depending on the mode of operation of the system. In addition, the system has the ability to transfer the generated packet of information to one of the terminal devices connected to this system.

The system also provides the possibility of priority servicing of terminal devices, which means that among the connected terminal devices it is possible to distinguish a number of devices that are serviced primarily, while ensuring the operation of the other terminal devices in their proper mode.

Along with the foregoing, the system sends back the information from the machine to the terminal devices, i.e. the reception of the anti-jam information packet from the machine, checking and issuing it to the terminal devices.

When exchanging information over a communication channel, the system changes the ability to re-request a received packet of information from the machine, if the latter was received distorted, and also to repeat the transmitted packet of information to the machine upon its request.

In addition to these capabilities, the system allows the exchange of information with another interface system of terminal devices, without the need for additional equipment costs.

The system works as follows. The symbol code formed by the terminal device 1, the bus 37 enters the block 10 analysis and communication with the terminal devices. In accordance with the control signals generated by the software tuning unit 9 on the clock signals bus 33, the analysis unit and associated with the terminal devices, the analyzer analyzes the received information by comparing the incoming code with the previous one. In accordance with the result of the analysis, the analysis unit 10 of communication with the terminal devices generates a signal on the control unit control bus buses 35 to initiate processing of the analysis results. Block 8 of priority processing initiation in accordance with signals received via buses 32 of control signals of a program setting block determining the priority of information processing for a given terminal, and results of analysis of incoming threads 35 generates a signal of priority processing of information to block 7 of firmware control via initiation priority processing, which, if there is a specified signal, determines the priority of the terminal and controls the system during reception and processing information. For this purpose, the microprogram management unit generates addresses by a specific sequence of microcommands stored in the persistent storage device 5 by generating instruction address counter 6 signals in 13 units. The generated addresses are read by busses 25 into the permanent storage device 5, where with the address, the micro-command code is read over the buses 24 into the micro-command register 4, where the code is saved for the execution time of the micro-command, after which the next micro-command is read. As a result of the execution of a micro-command, the code of which the microprogram control unit 7 reads from the register of micro-commands 4 via buses 15, one action of the algorithm for receiving, processing or issuing information occurs. So, for example, the symbol code received by the analysis and communication unit 10 with terminal devices and previously initiated (the previous processing is read from the buses 29 into the 2 operational registers block where it is stored during its processing time. Upon further reading of microcommands, the

7, the microprogram control generates control signals over the buses 16, as a result of which the code of the received symbol can be read by the RO buses 21 into the arithmetic logic unit. 1, where under the action of control signals arriving on the tires

14, information is checked, i.e., the received code is compared with various constants, the check bit addition is determined to evenness (oddness) and compared with the received one, the length of the received code is calculated, the shift is performed, etc. as a result, a decision is made on the reliability of the received code; the code of the received symbol on the tires 18 is read into block 2 of the oratio ratio.

8, depending on the processing results, if the symbol is received correctly, a jamming protection of the information packet is generated for transmission to the computer or transfer to another terminal, if such processing was determined as a result of the processing. At the same time, in order to form a jammed information packet, the code of the received symbol on the buses 19 in accordance with the signals produced by the unit

7 of the firmware, the bus 17 is recorded in the random access memory 3, where an information packet is formed. In the case of transfer of information to another terminal device, the code of the received symbol on buses 30 is read into the analysis and communication unit with terminal devices, from where buses pass 37 to the selected terminal. If during the verification of the information it is revealed that the symbol is incorrect, then it is canceled and the microprogram control unit 7, by reading the corresponding microcommands, can generate a response to the terminal device about the wrong network. The system also has the ability to control the logical format of the received document, while the generated packet of information can be read word by word from the random access memory 3 via the buses 22 to the partial operational registers 2, where processing is carried out similarly to that described above.

If, during the processing of information from one term, information from another terminal enters the analysis and communication unit with terminal devices, the processing priority of which is higher, then the priority processing initiation unit 8 generates the starting address of the microcommands of priority processing on buses 31 in the address of command 6, and on tires 12, the signal will be generated by the block 7. microprogram control of the highest processing priority. At that, the firmware control unit 7 stops the processing started earlier, saving the results into the unit (e operating registers, and starts processing the information from the priority terminal in accordance with the sequence of microcommands whose starting address was formed by the priority processing initiation unit 8. After the priority processing ends, the microprogram 7 management continues processing information interrupted by priority processing.

The priority of information processing from one or another terminal device can be changed. For this purpose, the firmware control unit 7 on the buses 16 generates a priority setting code for the desired terminal device, in which it indicates the analysis features, for the analysis and communication unit 10 with terminal devices and the priority level for the priority processing unit 8. The generated tuning code on buses 27 is rewritten into a software tuning unit 9, which, in accordance with the received code, controls the analysis and communication unit 10 with the terminal devices and the priority processing initiation unit 8 in accordance with the above. The firmware control unit 7 has the ability to monitor the state of the program setting block 9 by reading the tuning codes of the buses 28 into the block 2 operating registers with subsequent analysis in the device.

Information is exchanged with a computer through dedicated buses from a number of buses 37. In this case, information can be sent and received both in parallel and in sequential code and is determined by a sequence of readable microcommands. Due to the fact that the exchange with the computing machine is performed with the highest priority, information can be received and transmitted at high speeds (with a serial exchange of up to 2400 baud, while parallel with the speed of the input-output channel of the computer) - Exchange and primary processing information is carried out similarly to the above.

Information received from the computer by bus 37 via analysis block 10 and communication with terminal devices via bus 29 is recorded in block 2 of operational registers, from which, after analysis, the received symbol is recorded on bus 19 into random access memory, where a noise-protected packet received from the computer is formed information. At the end of the fermentation of the received information packet, the block 7 of the microprogrammed interference unit organizes the verification of the received anti-interference packet. For this purpose, the firmware control unit 7 to the Bushes 17 generates control signals providing a character-by-character reading of the packet from the random access memory 3 via the buses 22 to the block 2 bn & iznnyh registers, whence, when signals are available on the wrenches 16, ffo tires 21 are read into an arithmetic logic unit.

According to the results of the konurozop, the 7 micr block, the program control, in case of an incorrectly received information packet, generates the initial address of the sequence of microinstructions via the tires 13, as a result of which the microprogram control unit 7 using the cords 16 forms a request for retransmission to the computer in the block 2 operating registers a package that is read into the bus 10 through the tires 30, from where it enters the computer through the tires 37.

In the case of a correctly received packet of information, the microprogram control unit 7 generates signals over the buses 16, providing a character-by-letter reading of information from the random access memory 3 over the buses 22 and transmitting the read symbol over the buses 30 to the analysis and communication unit 10 with terminal devices, from where tires 37. symbol is transmitted to selected terminal

Claims (1)

Invention Formula A system for interfacing terminal devices with a computer, containing an arithmetic logic unit, operational register block, random access memory, microinstructions register, permanent memory, command address counter, the first output of which is connected to the input of a permanent memory device whose output is connected to the first input of the register of micro-commands, the second input of which is connected to the first output of the random access memory, the first output of the register of micro-commands soy dinene with the first input of the instruction address counter, the second output of the random access memory is connected with the first input of the operating register block, the first output of which is connected to the first input of the operational storage device, and the second output is connected to the first input of the arithmetic logic unit, the output of which is connected to the second input the block of operational registers, the second output of the instruction address counter is connected to the third input of the block of operational registers, characterized in that, in order to increase efficiency you system by providing primary information processing, the transfer between terminal devices connected to the system, the implementation of the priority service of the connected terminal devices, a program control unit, an analysis and communication unit with terminal devices connected to terminal devices, a program block settings, priority processing initiation block, the first output of which is connected to the first input of the firmware control block, the first The output of which is connected to the second input of the instruction address counter, the second output to the second input of the arithmetic logic unit, the third output to the fourth input of the operating registers block, the fourth output is connected to the second RAM input, the second input of the microprogram control unit is connected to the second the output of the register of microinstructions, the second output of the priority processing initiation block. is connected to the third input of the instruction address counter, the fourth input of which is connected to the first input of the block and analysis and communication with terminal devices, the second output of which is connected to the first input of the priority processing unit, the second input of which is connected to the first output of the program tuning unit, the second output of which is connected to the first input of the analysis and communication unit with terminal devices, the third output of which is connected to the fifth input of the operating registers block, the third output of which is connected to the second input of the analysis and communication unit with terminal devices, the third output of the priority processing initiation block It is connected to a sixth input of operational registers and four output is connected to the input of the program setting unit, the third output program setting unit is connected to the seventh input of operational registers. h