SU519703A1 - Selector channel - Google Patents

Description

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The invention relates to computing, in particular, the "organization of the structure of selector channels of input-output of electrode computers with microprogrammed control.

There are selector channels that contain a channel register assembly block, a data address counter, a byte counter, final gear request requests, a data preliminary gear request block, an OR element, a channel control block, a final state analysis block, a query feature register and an interface control unit. The first balancing output of the lowest is connected to the first input of the final state analysis block, the first output of the analysis block is correspondingly to the bary control inputs of the final hooking request block according to the data, the preliminary hooking request block but the ILP element and the request feature register. The information inputs and outputs of the query feature register, as well as the information inputs and outputs of the control unit, interface control unit, data address counter and byte counter are connected respectively to the device input data buses and the corresponding information inputs of the channel register assembly unit. Control input

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the latter, as well as the control inputs of the byte counter, the data address counter, the interface control block, the second control inputs of the final hook request block but the data, the preliminary hook link request block, the final state analysis block, and the characteristic registers are connected to the corresponding first control outputs of the channel control unit, the first, second and third control inputs of which are connected respectively to the device input control currents, the second control output of the control unit neither the interfaces and the control output of the data address counter. The first control output of the byte counter is connected to the third control input of the preliminary engagement request block but the second control output of the byte counter is connected to the fourth control input of the channel control block and the third control input of the final engagement request block of the data, the output of which is connected to the second input of the element

“OR, to the fifth control input of the channel control unit and to the third control input of the request attribute register. The fourth control input of the latter is connected to the second output of the final state analysis unit, information and other

The control outputs and inputs of the channel register assembly block, the data address counter, the OR element, the channel control block and the interface control block are connected to the corresponding information and control inputs and outputs of the device.

A disadvantage of the known selector channels is their low ippiOi performance when using the data meshing mode.

The purpose of the invention is to increase the speed of the selector channel in various modes.

This is achieved by the fact that the proposed selector channel additionally contains a block for analyzing the frequency of requests from an external device and an AND element whose output is connected to the third input of the OR element and the fifth control input of the query attribute register, and the first and second inputs of the AND elements are connected respectively, to the outputs of the block of requests for preliminary hooking according to the data and the block of frequency analysis of requests for the external ycTipoucTea, the first and second inputs of which are connected respectively to the first control output of the control unit ala and the second control output of the interface control unit. This allows data rates to be increased using the data meshing mode.

The block diagram of the selector channel is shown in the drawing, where 1 is the selector channel; 2 - the processor; 3 - high-speed external devices; 4 - random access memory; 5 - arithmetic-lopic device; 6, 7 - input information buses; 8 - output information buses; 9 — microprogram control unit; 10-channel register assembly unit; 11 - byte count; 12 - data address counter; 13 - block request for the final, data linking; 14 is a block request for preliminary engagement data; 15 - element 16 - channel control unit; 17 is an end state analysis unit; 18 - register of attributes of requests; 19 - interface control unit; 20 - element 21 - block analysis frequency requests external device; 22 — output control buses; 23 - output address bus.

The selector channel works as follows.

The data transfer operation starts with a special processor command that specifies the channel address and I / O devices and, using special control words, specifies the command code, the starting address of the main memory, the number of data bytes transferred, and other control features that are located in the channel registers and in a special memory, the image in the aggregate controls the channel words. Transmission of control information

between the processor 2 and the registers of the selector channel 1 is conducted through the block 10 of the registers of the registers, the input information buses 7 of the arithmetic logic unit, the arithmetic logic unit 5 and the output information buses 8 of the arithmetic logic unit.

Having received the necessary control information, the channel performs the initial

sampling an I / O device 3 via the interface control unit 19 and freeing the processor to execute other instructions.

Depending on the operation code set in the channel control block 16, the value of the 11 byte counter, the data buffer status in the interface control block 19, and the parity of the data address, the channel control block 16 generates signs of hardware suspension (transmission of one, two, etc. . bytes) and a request signal for data transmission, which via the request bus for data transfer of a group of output control buses 22 enters the processor firmware 9 of the processor. At this request, the processor operation on the execution of the current firmware after the completion of the next cycle "read-process -...- write pauses for the transmission cycle

data between the RAM and the channel. Since the word of the memory of the machine to which the channel in question is connected, consists of several bytes, depending on the signs of hardware suspension, one, two and other bytes are transferred between the interface control unit 19 and the operational device under the control of the channel block 16. 4 on the input or output information

buses 7 or 8 of the arithmetic logic unit, respectively, as well as transmitting the data address on the output address bus 23, generating control signals to perform the necessary read-write cycles, modify the data address and the byte counter.

When the channel finishes data transmission, in the final state analysis block 17 a final state processing request signal is generated, which, through the OR 15 element and the corresponding query bus of the output control bus group 22, enters the processor firmware control unit 9.

According to this request signal, depending on the status of the operation feature register in the channel control block 16, the device and channel status, and the reason for the formation of this request, in the register

The 18 request tags are set to the code of the corresponding processing firmware. The processing request signal in the processor interrupts the execution of the current firmware after the completion of the next cycle "read-process -...- write and switch to a special, in which the address of the next microcommand, which should have been executed, is stored in a special register (return register addresses) and the initial ad-5 res of the processing firmware is formed. This firmware records the contents of the processor registers in a special part of the operational memory and then, using the processing micro program code set in the request characteristics register 10 18, goes to the starting address of the microprogram processing this characteristic. The necessary actions take place (the end of an I / O operation, the command hooking, etc.) 15 and the modified or newly formed (when hooked) control word is written into a special part of the RAM. After this, the contents of the processor registers are restored from the special 20 part of the RAM and the interrupted firmware is executed, starting with the microcommand address stored in the return register. Performing the specified sequence of actions 25 takes a relatively long time. If a channel of the considered type and data hooking executes in the same Pattern, then it cannot ensure data hooking at the nominal data transfer rate between the external device and the channel. Consequently, a channel of this type has a limiting data transfer rate with the use of the meshing mode according to the data below the nominal data transfer rate without data transmission. The speed of data transmission using meshing can be increased if some of the actions related to the preparation of new control information 40 when meshing with the data are carried out Pre. In the channel it is organized as follows. At the stage of data transfer, when the channel finishes transmitting the data block and in the sign register of the operation of the channel control unit 16, the sign of data hooking is indicated, in block 14 of the pre-gearing request for data, a processing request is generated at that moment it remains to transmit, under the control of the current channel control word, such a number of bytes, the transmission of which to the channel will take the time required for this to: switch to the special 55 clock cycle, taking into account the maximum reading-O cycle time rabotka -...- record; memorize the contents of the processor registers in a special part of the RAM; read from the Special Memory to form in the registrar of the processor the address of the subsequent control word of the channel. Request For processing of pre-meshing on DAN through the element “AND P. element” OR 15, corresponding to the bar 65 of the request of the grupp of the output control pt. 22 It enters the block 9 of the firmware control of the Processor. According to THIS signal, the actions already described are performed in the processor, and in the register 18 of the signs of zapvosov the code of the preliminary engagement is set. Then, the processor registers are stored and the addresses of the subsequent channel control word are generated, and the waiting cycle of the 11 bytes counter is zero. With a zero 1 byte counter in block 13 of the request for final hooking, a direct hook signal is generated from the data, which goes to a block on the 16 l-channel, where the IT signal prohibits the generation of a data link request from the hardware signal. In the register 18 of the attributes of requests, a code of direct (kopeck) engagement is established according to the data, according to which a jump is made directly to the microharacter of engagement with the data. This firmware loads into the channel registers a new control word for the channel, the address of which is prepared by a member with preliminary preheating. After downloading a new channel control word, the data meshing firmware resets the final data request request signal, thereby disrupting the transmission of data under the control of the new channel control word, and restores the contents of the processor registers from a special part of the memory. Thereafter, the implementation of the Pre-firmware firmware continues. In the next page, if the I / O device completes the data transfer operation before the contents of the 11 byte counter becomes NULL, then the final state analysis block 17 excites the corresponding request signal, which blocks the generation of the preliminary engagement request signal and in the register 18 of signs Inquiries 1, the corresponding processing firmware code is inserted, from which the waiting cycle proceeds to the corresponding part of the processing MWK program. If the channel has a “pre-gearing mechanism that operates continuously and regardless of the frequency of the external device's requests for transmission of data, then when external devices that have a relatively low data transfer rate (less than the maximum data transfer rate with data linking without pre-engagement), pre-engagement stops the processor for a relatively long time, while satisfying the requests of other simultaneously operating channels for is held.

To reduce the effect of pre-hooking on the operation of other channels in the proposed channel, there is an external device request frequency analysis block 21, which constantly compares the frequency of requests for data transmission of external devices working in the channel with the maximum data transmission rate of the channel using data hooking without first hooking. . If the data transfer rate of the external device exceeds the limit data transfer rate of the channel with gearing, then a signal is generated at the output of the request frequency analysis block, which allows the pre-gearing request formed above and through the element 20 to perform the sequence described above. If the data transfer rate of the external device is equal to or less than the previous data transfer rate with clinging to the data, then the output signal of the request frequency analysis block prevents the preliminary request from entering the processor. In this case, normal saping is performed.

Claims (1)

Invention Formula The selector channel containing the channel register assembly block, the address counter of the data, the byte counter, the block of requests for final data hooking, the block of requests for preliminary data hooking, the OR element, the channel control block, the final state analysis block, the query feature register and an interface control unit, the first control output of which is connected to the first input of the final state analysis unit, the first output of which is connected respectively to the first escaping inputs of the final hook request unit e according to the data, the preliminary request block by data, the OR element, the register of request attributes, whose information inputs and outputs, as well as information inputs and outputs of the control unit, interface control unit, data address counter and byte counter, are connected respectively to the input information device buses and the corresponding information inputs of the assembly of the channel registers, the control input of which, as well as the control inputs of the byte counter, the data address counter, the control unit Interface, the second control inputs of the block query final engagement by the data request unit to the tentative engagement by the data analysis unit of the final state and the characteristic registers are connected to the corresponding first control output AM of the channel control unit, the first, second and third control inputs of which are connected respectively to the input control buses of the device, the second control output of the interface control unit and the control output of the data address counter, the first control the output of the byte counter is half connected to the third control unit of the zappos for pre-fusing, and the second control output of the byte counter is connected to the fourth control unit the input of the control unit kuna.p and the third l p-equalizing 0 input unit zapposop on the final gearing according to the data, the output of the Kotopogo is connected to the second “Element OR” FIFTH way. The control panel of the channel control unit and the third volume of the control input register of the inquiry feature register, the fourth control input of which is connected to the second output of the final state analyzer, the output of the channel register assembly assembly is connected to the first exhaust output of the counter, the data address is from secondly, the outputs of the OR element and the control unit of the channel, with the third and the block interface, with the 1- to the fifth output of the device, the corresponding inputs of the control unit of the channel, 5 Conceivers control unit. the byte counter and the data address are connected to the first terminal of the Device, the corresponding input of the channel control unit of the channel is connected to the second input of the Device, and the input of the control unit 0 of the interface with the third input of the device, characterized in that, with a speed increase, it additionally contains a block for analyzing the frequency of requests of the external device and the element "And, output 5 of which is 1 group with the third input of the element OR or the FIFTH control, its input of the register of features of requests, and the first and second inputs of the part-tement "And t are connected respectively to the outputs of the request block 0 preliminarily meshing with the data and the frequency analysis unit of the external device requests, the first and the inputs of which are connected respectively to the first control unit of the channel control unit 55 and the second control output of the interface control unit.