SU641438A1 - Device for interfacing main and auxiliary digital computers - Google Patents

Description

The main communication and auxiliary digital communication blocks are respectively the code inputs and device tracking inputs, the third code inputs of the communication blocks of the main and auxiliary digital computers are connected to the corresponding outputs of the output data switch, the first input output of the operating mode control unit is connected to the input-output of the block synchronization, the first, second outputs of the control unit of the simulation mode are connected respectively to the second and third control inputs of the output data switch, the control outputs b The communication terminals of the main and auxiliary digital computers are connected to the corresponding control inputs of the input switch.

The known device does not provide simultaneous exchange of information between the main machine and a set of auxiliary digital computers when issuing information from the base machine. In addition, the device does not provide the ability to control the correctness of information passing through the device.

All this does not allow for more efficient use of the digital computers included in the computing system and leads to a decrease in its performance.

The purpose of the invention is to increase speed and expand functionality by controlling data transfer and data exchange between auxiliary digital computers without the participation of the main digital computer. The goal is achieved by the fact that the device contains a subscriber feature register, an output command switch, a query register, a polling block, a pulse generator, an array length register, an address register, a current address block, a command and a queue, and the first, second, third inputs the outputs, the first and second inputs of the polling unit are connected respectively with the input-output registers}) and the query and subscriber feature register, with the second input-output of the operating mode control unit, with the output of the pulse generator, with the first the queue shaping block, the bit inputs of the query register are the device's query inputs, and the output is connected to the input of the pulse generator, the address register input and the first input of the array length register are connected to the second decoder output, the second, third, fourth inputs, the third and fourth outputs which, respectively, are connected with the control and code outputs of the input switch, with the output of the subscriber feature register, with the information inputs of the simulation and work data registers, the output of the work register This data terminal is connected to the third input of the control bits formation unit and the second information input of the output data switch, the first, third, third inputs, output and input-output of the command FOROR unit are connected respectively to the first outputs of the current address and register register adre- a, with the first output of the synchronization unit, with the information input of the output command switch, with the input-output unit of the formation of the control bits, the first, second outputs of which are connected respectively to the third and The Fourth information of the output data switch inputs, a first, a second input and a second output current address generating unit are connected respectively to the second output of the address register, a first output and

the second input of the array length register, the second output of which is connected to the inputs of the subscriber feature register and the queue builder, the second to fourth outputs of which are connected respectively to the enable input of the input switch and the second control inputs of the first, second and third communication blocks of auxiliary digital computers, and the fourth code inputs of the communication units of the main and auxiliary digital computers are connected to the corresponding outputs of the output command switch, the control input of which is connected to the third output of the block operating mode control.

The block diagram of the device is shown in the drawing.

0 A device for interfacing the main and auxiliary digital computers contains: decoder 1, register of 2 signs of subscribers, register of 3 requests, block 4 of control of the operating mode, generator of 5 pulses, block

. 6 synchronization, block 7 of communication of the main digital computer, blocks 8-10 of communication of auxiliary digital computers, block 11 of the simulation mode control, simulation data register 12, working data register 13, array length register 14, address register 15, block 16

polling, data output switch 17, command output switch 18, input switch 19, check bits generation unit 20, current address generation unit 21, command generation unit 22, queue generation unit 23 with output 24.

Positions 25 (, -25j denote the request, device inputs, positions 26o-26j, 27j, -27z - code inputs, positions of the signals of the tracking signals, positions 29o-29j outputs of the ready signal, positions 30, 30, 30 - Blj - code outputs of the device.

The device works as follows.

Information is exchanged between the main and auxiliary machines. The device operates in four modes: in the mode of transmitting information from the main machine (mode 1), in the mode of receiving information from the main machine (mode

II), and also in the modes of imitation of transmission and reception of information by the main machine (modes HI, IV). Moreover, in modes I and I, any set of auxiliary machines can participate in the exchange simultaneously, in modes IV auxiliary machines are served in the order received by one application for the exchange of the main digital computer.

When generating in memory any MaaiHHbi array intended for transmission and readiness to issue information, the machine sends an exchange for the exchange in the form of one binary digit to the corresponding register bit 3.

A non-zero register code 3 is a prerequisite for switching on a generator of 5 pulses. The generator 5 will continue to excite with a given frequency block 16 of the survey. Generator 5 is turned on when the first request for rotation is received.

The polling unit 16, triggered by the generator 5 with a certain frequency, polls registers 2 and 3 and, depending on their state, gives the necessary recommendations for organizing the exchange of information to blocks 4 and 23.

After being started from generator 5, block J6 analyzes the state of register 3. If there is an exchange request from any machine, the polling unit performs the actions to start the exchange. In this case, if there are exchange requests from the main machine, regardless of the presence of exchange requests from auxiliary machines, mode I is started. Block 16 informs block 23 of the presence of exchange requests.

Block 23 forms a queue with the highest priority of the main machine.

In mode 1, block 23 starts the switch 19, thereby providing the information path from the main machine. First, information from registers 2, 14 and 15 should be output from the main machine. Unit 16 analyzes the state of register 2. Information in this register can only be written from the main machine, which is provided by decoder 1. If present in register 2, for example, signs and the second auxiliary machines, block 16 issues the corresponding code to block 4. Upon receipt of this code, block 4 controls the issuance of data and commands to blocks 8, 9, switches 17, 18.

Unit 6 synchronizes the process of the switches 17, 18.

The exchange process itself begins after the registers 14 and 15 receive information. Block 21 generates a memory address into which the next information word from register 13 will be written depending on the state of registers 14 and 15. After generating the next address, a signal is output to register 14 its value is one. When registering the value of register 14 to zero, a signal is output to register 2, extinguishing the signs of subscribers assigned to the exchange, as well as to block 23, which deletes the main machine from the queue and allows the next n queue to be switched to the auxiliary machine by opening the corresponding circuits of the switch 19. Blocks 4 and II, in turn, will ensure the opening (closing) of the circuits of the switches 17. 18.

The generated memory address of the auxiliary machines is stored in block 21. Block 22 generates a command to write the contents of the register 13 (or 12 in mode P) to the memory of the corresponding machines. The check bits are formed by block 20 according to the signal of generator 5. The same signal synchronizes the output via the switches 17, 18 of the information word from the register 13 and commands from the block 22 to blocks 8 and 9 and further to the first and second auxiliary machines. Switches 17, 18 provide coordination of the formats of transmitted codes.

Information to register 13 arrives at a predetermined frequency after receiving the address of register 13 by the decoder. If there is no update of register 13, the last contents of this register will be transferred to the auxiliary machines assigned to the exchange. In particular, this makes it possible to check the transmission path of information by sending the selected standard codes to register 13, followed by software check summation in the designated machines. To check, you can set a pre-set code and the length of the array and compare with those obtained during transmission.

Mode II is possible if an exchange request is received to register 3, and the indicated auxiliary machine, for example, the first one, is queued for exchange with the main machine. In this case, the unit 23 issues to the unit 8 a destination (readiness) signal for exchange via the bus 29i and opens the circuits of the switch 17, through which the information of the first auxiliary machine enters. In this information. in register 2 is missing. Block 16 issues a code to block 4, having received which block 4 opens the corresponding circuits of the switch 17, 18. By the signal from block 4, block 11 will operate in the same way as in mode I. The information exchange between the first auxiliary machine and the main machine then occurs as in mode I, with registers 13, 14, 15 being filled with information words transmitted from the first auxiliary machine.

.After transferring the entire array from the first auxiliary machine to the main machine as in mode I, a signal is sent to register 2 and blocks 23 and 23, and block 23 will cross out the first auxiliary machine from the queue and allow the next auxiliary machine to be exchanged by opening the corresponding circuits switch 19.

In mode III, a simulated information output by the main machine to the designated auxiliary machines is performed. To simulate the exchange, the register 12 must be filled out, and also issued by the SUD indicating the direction of the simulation to block 11. Moreover, the information in these blocks can be entered from any machine, primary or secondary. In order to fill these blocks, a request must first be made from a machine that transmits information to addressable blocks.

In order to simulate the exchange, block 4 will open the circuits of the switch 17, 18 for issuing information to machines. Valuable to imitation according to register 2, as in mode I, block 11 will open circuits of switch 17, through which information comes from register 12. In this case, circuits of switch 19 that receive information from the main machine will be closed, since the request from the main cars did not arrive. In fact, the auxiliary machines will exchange information not with the main machine, but with the register 12. The main machine actually turns off from the computational circuit before the permit code enters unit P. This can be done by any of the auxiliary machines.

When exchanging with register 12, the code stored on the Fiero is transmitted to the first and third auxiliary machines. In the event that the code for this register was issued, for example, from the first auxiliary machine, this code will be transmitted to the first and third auxiliary machines, since the corresponding circuits of the switch 17 are opened. Thus, it becomes possible to exchange information between the auxiliary machines via register 12 and receiving the code (in the first auxiliary machine 1) transmitted by the same machine to register 12.

In mode IV, for example, when simulating the transfer of information from the first auxiliary machine to the main machine, the word transmitted from the first auxiliary machine is set on register 12, and the code of the simulation type is set by unit P. The exchange request is sent by the main machine. AT . only the main machine is involved in the computational circuit. Using new elements: subscriber feature registers, requests, array length, generator address, polling block, address and command generation blocks, queue shaping unit, as well as the introduction of new connections between known and newly introduced elements distinguishes the invention from the known device, t . to. allows. to increase the performance of the computing system, to control the transmission path of information, and also allows for the possibility of cancellation of information between the compressing digital computers through the imitation) 1st reg. data page.

The productivity of the device is increased three times when information is transmitted to auxiliary machines from the main one due to the possibility of transmitting information to several machines simultaneously. In addition, the device forming a command that records information from the working (imitation) data register allows reducing the time for writing information in the memory of any of the digital computers, since there is no need to take the processor time to read a word.

The functionality of the device is expanded by checking the information transmission path by sending the selected standard codes to the simulation rep. data hub with subsequent program check summation in the digital computers assigned to the exchange or readout — the code of the same digital computer that addressed this register was sent to the simulation data register.

Claims (2)

Invention Formula A device for interfacing the main and auxiliary digital computers (DVR) containing a decoder, the first output of which is connected to the first input of the control mode and simulation module,. Simulation data register, the output of which is connected to the first information input of the output data switch and to the first input of the check bits generation unit; synchronization unit, the first output of which is connected to the control inputs of the simulation and work data registers; operating mode control block, first, second and the third outputs of which are connected respectively to the second input of the simulation mode control unit, to the second input of the check bits generation unit and to the first control input of the output bit of the data switch, the communication unit of the main digital computer, the first, second and third communication units of the auxiliary digital computers, the first control inputs of which are connected to the second output of the synchronization unit and the input switch, and nepBi ie the code outputs of the communication unit of the main digital computer and communication units The auxiliary digital computers are connected to the corresponding information inputs of the input switch, the second, third code outputs, the outputs of the ready signals of the communication blocks of the main and auxiliary digital computers, are respectively the code outputs and the outputs are ready These devices, the first and second code inputs and the tracking signal inputs of the HVDC communication blocks) HV () TH and VSPO of the digital computers are respectively the code inputs and device tracking inputs, the third code inputs of the primary and auxiliary digital communication modules are connected to the corresponding outputs of the output switch data, the first input-output of the operating mode control unit is connected to the input-output of the synchronization unit, the first, second outputs of the simulation mode control unit are connected to the second and third pack, respectively equal inputs of the output data switch, the control outputs of the communication blocks of the main and auxiliary digital computers are connected to the corresponding control inputs of the input switch, characterized in that, in order to increase speed and enhancement of the functionality by transmitting data paths and exchanging data between the auxiliary digital computers without the fate of the main digital computer, it contains the subscriber feature register, the output command switch, the query register, the polling unit, the generator / pulses, the length register array , the address register, the current address block, the command and the queue, the first, second, third inputs-outputs, the first and second inputs of the polling unit are connected respectively to the inputs-outputs of the query register and subscriber feature register, to the second input-output of the control unit the operating mode, with the output of the pulse generator, with the first output of the queue builder, the bit inputs of the request register are the device's request inputs, and the output is connected to the input of the pulse generator, the address register input and the first input The length register of the array is connected to the second output of the decoder, the second, third, fourth inputs, the third and fourth outputs of which are connected respectively to the control and code outputs of the input switch, to the output jKTHCTpa of subscriber signs, and information and imitation inputs of the simulation (H) and working registers data, the output of the data register is connected to the third input of the block forming the check bits and with the second information input of the output data switch, the first, second, third inputs, output and input-output unit f The command is connected, respectively, to the first outputs of the current address and address register generation unit, to the first output of the synchronization unit, to the information output of the command switch, to the input-output of the control bits generation unit, to the first output, the second outputs of which are connected respectively to the third output. the fourth information inputs of the output data switch, the first, second inputs and the second output of the current address generation unit are connected respectively to the second output of the address register , with the first output and the second input of the array length register, the second output of which is connected to the inputs of the subscriber feature register and the queue generation unit, the second to 4th outputs of which are connected respectively to the enabling input of the input switch and the second control inputs of the first, second and third communication units of auxiliary digital computers, and the fourth code inputs of communication units of the main and auxiliary digital computers are connected to the corresponding outputs of the output command switch, the control input of which is connected to the third m output operation mode control unit. Sources of information received by attention during the examination 1. USSR author's certificate No. 481895, c. G 06 F 3/04, 1972. 2. USSR author's certificate number 437075, cl. G 06 F 15/16, 1974.  -ss-ifir s