JPH0782462B2 - Multi-byte data protection system in standby RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to turning on a main power source of a microcomputer,
In a microcomputer system that has a standby RAM that operates by being supplied with power from a separate system power supply regardless of whether it is off or off, the writing operation is stopped by turning off the main power supply while writing multi-byte data to the standby RAM. The present invention relates to a protection method for multi-byte data in standby RAM that can restore normal data even if the byte data is destroyed.

[Conventional technology]

2. Description of the Related Art In recent years, electronic devices incorporating a microcomputer system have been actively developed. Among them, a standby system that operates with a minute current supplied from a separate power supply regardless of whether the main power supply of the microcomputer is on or off. An increasing number of electronic devices have adopted a microcomputer system equipped with RAM.

As such an electronic device, there is an electronic control device for an automobile that controls an internal combustion engine, a transmission, etc. of the automobile. In the case of this equipment, the main power is supplied from the ignition switch system to the microcomputer system, and the separate system power taken out from the car battery without passing through the ignition switch is supplied to the standby RAM, after the driver turns off the ignition switch. But standby
It is configured to retain the contents of RAM. The standby RAM uses its non-volatility to store various abnormal mode information that is useful for diagnosis at the dealer and the correction amount for optimization of the control amount learned to absorb the variation of each vehicle. Contains important data.

Therefore, it is one of the important items in designing control equipment to prevent the above important data stored in the standby RAM from being destroyed. The following methods have been proposed or put into practical use.

Conventional method 1 When the ignition switch is turned off, that is, when the main power supply is turned off, the reset signal of the microcomputer is activated (ACTIVE) to prevent uncertain operation of the microcomputer when the main power supply voltage is low, and the program is mainly in standby due to runaway. Prevents the destruction of data in RAM.

Conventional method 2 Immediately before the reset signal of the microcomputer becomes active, an external interrupt signal is generated by hardware, and a dummy instruction is executed in the interrupt program until the reset signal becomes active, and the standby RAM
Prevents data in the standby RAM from being destroyed by not writing to the RAM.

[Problems to be solved by the invention]

By the way, the data in the standby RAM includes 1-byte data and multi-byte data having a single meaning with a plurality of bytes. In the case of the latter multi-byte data, for example, 16-bit data in an 8-bit microcomputer, two store instructions are executed when this is written in a continuous 2-byte area of the standby RAM, while the microcomputer When the operation stops, the 2-byte data has been destroyed.

For example, the address n of the standby RAM is for the upper byte,
There is 2-byte data for the lower byte at address n + 1, the value of the upper byte before updating is "00000001", and the value of the lower byte is "00000000", that is, "25" in decimal notation.
It is assumed that the data of "6" is stored. This data 10
To rewrite the value of the upper byte to "00000000" and the value of the lower byte to "11111111" in order to rewrite the value of "255" in decimal notation, for example, the command STA n \ 00 STA n + 1 \ FF Although the column is executed, if the write operation is stopped by the reset by turning off the ignition switch immediately after writing the area of the address n, the value of the address n + 1 remains the original “00000000”, so that the address n and the address n + 1. The data expressed by 2 bytes is "000" in decimal notation, which is "255" off the true value.

Although the conventional methods 1 and 2 described above can prevent the destruction of 1-byte data in the standby RAM,
The multi-byte data as described above cannot be prevented from being destroyed and cannot be restored to a normal value.

The present invention has been made in view of such circumstances, and an object thereof is to stop the writing operation by turning off the main power supply during writing of multi-byte data in the standby RAM.
It is to provide a multi-byte data protection method in standby RAM that can restore the multi-byte data to a normal value.

[Means for solving problems]

In order to achieve the above object, the present invention operates by receiving power supply from a separate system power supply regardless of whether the main power supply is on or off, and operates in an arithmetic processing unit via a data bus, an address bus, and a read / write signal line. Connected standby RAM
In the microcomputer system having: an address holding unit that operates by the separate power supply, holds the address on the address bus immediately before the arithmetic processing device stops the operation by turning off the main power supply, and the separate power supply. A read / write signal holding unit that operates and holds the signal on the read / write signal line immediately before the arithmetic processing device stops its operation when the main power supply is turned off; Data processing means for holding all bytes of the multi-byte data which was about to be written immediately before the device stopped its operation when the main power supply was turned off. / The write signal is held in the write signal holding means and the number of addresses held in the address holding means is large. When the condition that the byte data storage address is satisfied is determined, and when the condition is satisfied, a process of matching the corresponding multibyte data in the standby RAM with the multibyte data stored in the data storage means is performed. Is configured to do.

[Action]

The main power is turned off while the processor is writing multi-byte data in the standby RAM, and the standby RA
If the multi-byte data in M is destroyed, read /
Since the write signal holding unit holds the write signal and the address holding unit holds the address corresponding to the multi-byte data storage address, the arithmetic processing unit writes the multi-byte data at the next main power-on. When the operation is stopped, the multibyte data in the corresponding standby RAM is restored by performing processing so that the multibyte data matches the multibyte data held in the data holding means.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing an example in which the present invention is applied to a vehicle-mounted microcomputer system in which multi-byte data is only 2-byte data, 1 is a microcomputer, 2 is an automobile battery, Reference numeral 3 is an ignition switch, 4 is a constant voltage circuit for supplying main power, 5 is a constant voltage circuit for supplying standby power, 6 is a reset signal generating circuit, and 7 is a clock generating circuit.

The microcomputer 1 is a processing unit (MPU) 10
A ROM 11, a RAM 12, a standby RAM 13, an input / output port (I / O port) 14, a gate control circuit 15, a first data register 16, a second data register 17, an address latch circuit 18, A read / write signal latch circuit 19,
Gate circuit (G) 20-23, 30, 31 and latch signal generation circuit
24 and a clock control circuit 32, and the MPU 10 and peripheral circuits include the MPU 10 data bus DB and address bus AB as required.
And a control bus CB including a read signal line and a write signal line are connected to each other.

The output voltage Vcc of the constant voltage circuit 4 activated by turning on the ignition switch 3 is applied to the reset signal generating circuit 6, the clock generating circuit 7 and the main power supply terminal 25 of the microcomputer 1, and the reset signal generating circuit 6 outputs the signal. When the voltage Vcc is on and off, a reset signal R is generated and applied to the reset terminal 26 of the microcomputer 1. The voltage Vcc applied to the main power supply terminal 25 is MPU10, R
The reset signal supplied to the OM 11, the RAM 12, the I / O port 14, the gate control circuit 15 and the like and applied to the reset terminal 26 is supplied to the latch signal generation circuit 24 and the MPU 10. Further, the clock generated by the clock generation circuit 7 is input to the clock terminal 27 of the microcomputer 1, and the internal clock control circuit 32 generates the system clock Φ, which is supplied to the latch signal generation circuit 24 and each part in the microcomputer 1. Supplied.

Since the constant voltage circuit 5 is directly connected to the automobile battery 2,
It operates regardless of whether the ignition switch 3 is on or off, and applies the standby voltage Vs to the standby voltage terminal 28 of the microcomputer 1. The standby voltage Vs applied to this terminal 28 is the standby RAM 13, the first data register.
16, supplied to the second data register 17, the address latch circuit 18, and the read / write signal latch circuit 19.

The gate control circuit 15 in the microcomputer 1 decodes the address on the address bus AB, and the gate circuits 20 ...
The opening / closing control of 23, 30, 31 is performed.

Further, the first and second data registers 16 and 17 in the microcomputer 1 store the upper byte and the lower byte of the 2-byte data to be rewritten when the MPU 10 rewrites the 2-byte data in the standby RAM 13. It is a register for preserving it, and since it operates at the standby voltage Vs, its contents are retained even while the ignition switch 3 is off. For writing to the first and second data registers 16 and 17, the addresses corresponding to the first and second data registers 16 and 17 are sent to the address bus AB, and the gate control circuit 15 causes the gate circuit.
20 and 21 are opened, the gate circuits 30 and 31 are opened, and the read / write signal line of the control bus CB is set to the write state. Also, the first and second data registers 1
The contents of 6,17 can be read from the MPU, open the gate circuits 20,21,30,31 in the same manner as above, and open the control bus C
The B read / write signal line is set to the read state.

The latch signal generation circuit 24 has a latch signal L that becomes, for example, “0” at the first fall of the system lock Φ after the reset signal applied to the reset terminal 26 becomes low active.
The latch signal L is given to the address latch circuit 18 and the read / write signal latch circuit 19.

The address latch circuit 18 latches the contents of the address bus AB at the timing of the latch signal L, and the read / write signal latch circuit 19 determines the state of the read / write signal line of the control bus CB at the timing of the latch signal L. It is the one to latch. Since both of them operate at the standby voltage Vs, their contents are held even when the ignition switch 3 is off. Address and read / write signal latch circuit latched in address latch circuit 18
In the state held in 19, the addresses corresponding to the address latch circuit 18 and the read / write signal latch circuit 19 are sent to the address bus AB of the MPU 10 to output the gate control circuit 15
By opening the gate circuits 22 and 23 by, it becomes possible to read from the MPU 10 via the data bus DB.

FIG. 2 is a diagram showing an example of data arrangement in the standby RAM 13, in which 16 bytes C000 to C00F of the address space allocated to the standby RAM 13 are allocated to a total of 8 2-byte data storage areas, and the others are 1 An example of allocation to the byte data storage area is shown below. In the upper byte of each 2-byte data, the least significant bit is stored in an even-numbered address, and the lower byte is stored in an odd-numbered address.

FIG. 3 shows a processing example when the MPU 10 updates 2-byte data in the standby RAM 13 according to a program stored in the ROM 11, and FIG. 4 shows a processing example immediately after being started by turning on the ignition switch 3. . Less than,
The operation of this embodiment will be described with reference to the drawings.

MPU10 follows various programs stored in ROM11,
As is well known, a signal applied to the input / output terminal 29 of the microcomputer 1 is read through the I / O port 14, various operations are executed according to the signal, and various control signals obtained by the operation are I / O.
It is output to the outside through O port 14.

In such a process, 2 in the standby RAM 13
In the past, when it was necessary to update the byte data, each byte of the 2-byte data was immediately written to the standby RAM 13, but in the present embodiment, the standby RAM 13 is written.
Before writing to, first write the 2-byte data to be written
1, stored in the second data registers 16 and 17. This is the third
This is performed as shown in the figure. That is, the MPU 10 has the update address of the standby RAM 13 of C000 to C00F in the above example.
If the above condition is true, it is determined that the 2-byte data has been updated (S1), and the upper byte of the 2-byte data to be written is written to the first data register 16 via the data bus DB and the gate circuit 20 ( S2), then the lower byte on the data bus
Write to the second data register 17 via the DB and gate circuit 21 (S3). Then, as in the conventional case, the corresponding 2-byte data in the standby RAM 13 is rewritten (S4).

Rewriting of the 2-byte data is performed, for example, one byte at a time so that the upper byte is rewritten first, and then the lower byte is rewritten. Therefore, if the operation of the MPU 10 is stopped due to the turning-off of the ignition switch 3 in the middle of the operation, the 2-byte data will be destroyed as described above.

FIG. 5 shows the state of each part when the reset caused by turning off the ignition switch 3 is applied to the microcomputer 1 during the rewriting of the first 2-byte data stored in the addresses C000 and C001 of the standby RAM 13. It is a timing chart.

When the ignition switch 3 is turned off, the reset signal R output from the reset signal generating circuit 6 becomes "0" after a predetermined time, and the MPU 10 completes the machine cycle if it is executing during one machine cycle. To stop the operation. Therefore, as shown in FIG. 5, if the machine cycle is a rewriting cycle of the above-mentioned byte of 2-byte data, the operation is stopped after the above-mentioned rewriting of the byte, and the rewriting of the lower byte is not executed.

On the other hand, when the reset signal R becomes "0", the latch signal L output from the latch signal generating circuit 24 becomes "0" at the next falling edge of the clock, and at this timing, the address latch circuit 18, read / write The signal latch circuit 19 performs a latch operation. Therefore, in the address latch circuit 18,
Address C000 being output to address bus AB at that time
Is latched, and the read / write signal latch circuit 19
The write state will be latched and will be retained even after the MPU 10 stops operating. Further, as described above, the MPU 10 stores the upper byte of the 2-byte data of the addresses C000 and C001 to be rewritten in the first data register 16 and the lower byte in the second data.
Since the data is written in the data register 17, the 2-byte data is retained even after the operation of the MPU 10 is stopped.

After that, when the ignition switch 3 is turned on, MP
U10 executes the processing of FIG. 4 in its initial processing.
First, the contents of the read / latch signal latch circuit 19 are read through the gate circuit 23 (S10), and it is determined whether or not it is in the write state (S11). If it is not in the write state, the process proceeds to the next process, but if it is in the write state, the gate circuit 22
Read the contents of the address latch circuit 18 via (S1
2). And this read address is the standby RAM13
It is determined whether or not it corresponds to the 2-byte data area in (S1
3) If the area is other than that area, proceed to the next process, but if the area is a 2-byte data area, the corresponding 2-byte data in the standby RAM 13 is stored in the first and second data registers 16 and 17. A process for matching the byte data is executed (S14 to S18).

In the case of the timing chart shown in FIG. 5, the read / write signal latch circuit 19 holds the write state, and the address latch circuit 18 stores the upper byte address C000 of the first 2-byte data. , MPU10 will perform steps S14-S18.

Various kinds of processing are conceivable as the processing for matching the corresponding 2-byte data in the standby RAM 13 with the 2-byte data stored in the first and second data registers 16 and 17, and the present invention is limited to that method. It is not something to do,
As an example, Fig. 4 adopts the method of unconditionally writing the contents of the first and second data registers 16 and 17 to the corresponding addresses of the standby RAM 13 when the operation is stopped during the rewriting of the 2-byte data. is doing. Further, as a method of knowing the write destination address of the first and second data registers 16 and 17, the address stored in the address latch circuit 18 and the least significant bit thereof are determined to be even or odd. That is, as described above, since the least significant bit of the upper byte of the 2-byte data is stored in the even address and the lower byte is stored in the odd address, the MPU 10 operates in the address latch circuit 1.
When the least significant bit latched in 8 is an even number, the contents of the first data register 16 are written to the area of the standby RAM 13 corresponding to the latch address, and then the contents of the second data register 17 are set to the latch address + 1. Write to the area of the corresponding standby RAM 13 (S14 to S16), and conversely, if the least significant bit latched by the address latch circuit 18 is an odd number, the contents of the first data register 16 will be the standby address corresponding to the latch address-1. After writing to the area of RAM13,
The contents of the second data register 17 are written in the area of the standby RAM 13 corresponding to the latch address (S14, S17, S18). Therefore, in the case of the timing chart shown in FIG. 5, the address latch circuit 18 latches the address of C000, and the least significant bit thereof is an even number.
The contents of 16 are stored in the C000 area of the standby RAM13,
The contents of the second data register 17 is C001 of the standby RAM13.
Address C001 stored in the area
The content of is restored to its true value.

In the process of FIG. 4, the first and second data registers 16,1
The contents of 7 and the contents of the corresponding standby RAM 13 are not compared, but the contents of the first and second data registers 16 and 17 are written, but it is checked whether the contents of the two match or not. Alternatively, only when they do not match, only the unmatched bytes or both bytes may be written.

FIG. 6 shows a circuit of an embodiment of the address latch circuit 18,
An example of 16 flip-flops corresponding to the number of bits of the address bus operating at the standby voltage Vs is shown.
The latch signal L is input to the clock terminal CLK of each flip-flop 60, and the address bus AB is input to the data input terminal D.
The signals of the corresponding bit lines A _{0 to} A ₁₅ are input, and the latch signals A ₀ ′ to A ₁₅ ′ of each bit are taken out from the output terminal Q.

FIG. 7 is a circuit diagram of an embodiment of the read / write signal latch circuit 19, in which one flip-flop 70 operating at the standby voltage Vs is used, the latch signal L is input to its clock terminal CLK, and the data input is performed. Control bus to terminal D
The state (R / W) of the read / latch signal line of CB is input and the latch signal R / W 'is taken out from the output terminal Q.

FIG. 8 is a circuit diagram of an embodiment of the first data register 16, and the second data register 17 can have the same structure. The data register of this embodiment has a standby voltage
A gate circuit 81 which uses eight flip-flops 80 operating at Vs and takes the logical sum of the system clock Φ and the read / write signal R / W30 from the gate circuit 30 shown in FIG. The output is input, each data bit line D _{0 to} D ₇ in the output of the gate circuit 20 is input to the data input terminal D, and the output terminal Q is connected to the data bit lines D _{0 to} D ₇ via the driver 82. It is a thing. Driver 82 read /
When the write signal R / W30 is read, it is turned off, and when it is written, it is turned on. As another embodiment of the data holding means for holding all the bytes of the 2-byte data which the MPU was about to write immediately before stopping its operation,
A configuration is conceivable in which U10 writes the 2-byte data to be written into another register operating with the main power supply and latches the content in another register operating with the standby voltage Vs at the timing of the latch signal.

FIG. 9 is a circuit diagram of an embodiment of the latch signal generating circuit 24. One flip-flop 90 is used, and the system clock Φ of FIG. 5 is input to its clock terminal CLK via an inverter 91 to input data. The reset signal R is input to the terminal D, and the latch signal is taken out from the output terminal Q via the inverter 92.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and various other additions and changes are possible, and multi-byte data other than 2-byte data, for example, 3-byte data, 4-byte data. It is also applicable to etc.

〔The invention's effect〕

As described above, the present invention provides the data holding means, the address holding means, and the read / write signal holding means with what operation was being performed immediately before the arithmetic processing unit stopped its operation due to the turning off of the main power supply. Keep it
Processing to match the multibyte data in the corresponding standby RAM with the multibyte data held in the data holding means when the main power supply is turned on and if it is determined from the stored contents that the operation stopped during the writing of the multibyte data Even if the multi-byte data in the standby RAM is destroyed, it can be restored to the true value.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of data arrangement in the standby RAM 13, and FIG. 3 is an example of processing when the MPU 10 updates 2-byte data in the standby RAM 13. Flow chart, FIG. 4 is a flow chart of an example of processing performed by the MPU 10 immediately after the ignition switch 3 is activated by turning on the ignition switch 3, and FIG. 5 is a reset caused by turning off the ignition switch 3 during rewriting of 2 bytes of data in the standby RAM 13. 6 is a timing chart showing the state of each part when applied to the microcomputer 1, FIG. 6 is a circuit diagram of an embodiment of the address latch circuit 18, FIG. 7 is a circuit diagram of an embodiment of the read / write signal latch circuit 19, FIG. 8 is a circuit diagram of an embodiment of the first data register 16, and FIG. 9 is a circuit diagram of an embodiment of the latch signal generating circuit 24. In the figure, 1 ... Microcomputer, 2 ... Car battery, 3 ... Ignition switch, 4 ... Main power supply constant voltage circuit, 5 ... Standby power supply constant voltage circuit, 6 ... Reset signal generation circuit , 7 ... Clock generation circuit, 10 ... Arithmetic processing unit (MPU), 11 ... ROM,
12 …… RAM, 13 …… Standby RAM, 14 …… Input / output port (I / O port), 15 …… Gate control circuit, 16 …… First data register, 17 …… Second data register, 18 …… Address latch circuit, 19 ... Read / write signal latch circuit, 20-23, 30, 31 ... Gate circuit, 24 ... Latch signal generation circuit.

Claims (1)

[Claims] 1. A standby RAM that operates by receiving power from another system power supply regardless of whether the main power supply is on or off and is connected to an arithmetic processing unit through a data bus, an address bus, and a read / write signal line. In the microcomputer system having, an address holding unit that operates with the separate system power supply and holds an address on the address bus immediately before the arithmetic processing device stops the operation by turning off the main power supply, and the separate system power supply A read / write signal holding unit that operates and holds the signal on the read / write signal line immediately before the arithmetic processing device stops its operation when the main power supply is turned off; All bytes of the multi-byte data that was about to be written immediately before the device stopped operating due to the main power being turned off The arithmetic processing unit stores a write signal in the read / write signal holding unit and stores an address held in the address holding unit in multi-byte data when the main power supply is turned on. When it is determined that the condition corresponding to the address is satisfied, and when the condition is satisfied, processing for matching the corresponding multi-byte data in the standby RAM with the multi-byte data stored in the data storage means is performed. A protection method for multi-byte data in standby RAM characterized by being configured.