JP2781779B2 - Branch control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to instruction execution control of an information processing system, and more particularly to a non-pipeline processing type branch control circuit.

[0002]

2. Description of the Related Art As a method of accelerating the branch processing of a computer, there is provided a pre-branch address table and a post-branch address table described in Japanese Patent Application Laid-Open No. 2-173825 (hereinafter referred to as Conventional Example 1). As a method for deleting the fetch time of a program, a conventionally known method is described in “Microprogramming” (published by Sangyo Tosho Co., Ltd.). 45-P. There is a method (hereinafter, referred to as a next address method) in which an address portion indicating the microinstruction to be executed next is provided in the microinstructions of the microprogram described in 46. The next address method will be described later.

First, Conventional Example 1 will be described with reference to a block diagram of FIG. 10 and schematic diagrams showing program examples of FIGS. 11 and 12. 10, the circuit includes a memory 1, an instruction buffer 2, a decoder / execution unit 3, a program counter unit 4, and a branch table unit 904.

[0004] The memory 1 is controlled by the program counter unit 4.
The storage address of the instruction to be executed next is specified, read into the instruction buffer 2 (hereinafter referred to as fetch processing), and the decoder / execution unit 3 decodes and executes the instruction. The branch table section 904 stores the pre-branch address table 9
12, a post-branch address table 911 and an address comparator 906, and address data is written into each table using a dedicated instruction before a desired branch operation.
The program counter unit 4 includes a program counter 9, an incrementer 7, and a selector 8, and a selector 8
According to the comparison result of the address comparator 906, the incrementer 7 is selected when there is no match, and the address table after branching is selected when there is a match.

In the case of a normal non-branch instruction, the address data of the program counter 9 is supplied to the memory 1 and to the incrementer 7, and the address data incremented by the incrementer 7 is written to the program counter 9 via the selector 8. Will be returned. By repeating this operation, instruction codes on the memory 1 are sequentially fetched. In the case of a branch instruction, the address data on the pre-branch address table 912 and the address data of the program counter 9 are compared by the address comparator 906, and if they match, the matched pre-branch address table 912
Is set in the program counter 9 via the selector 8 after the branching in the address table 911 corresponding to. The branch operation is realized by the above operation.

Now, consider the case where the program shown in FIG. 11 is executed. Processes 1 to 6 represent any instruction including a branch instruction, and JUMPnnnnH represents a branch instruction to address nnnnH. There is a branch instruction at address 0002H,
Before the execution of the address 0002H, “0001H”, which is the pre-branch address, is stored in the pre-branch address table 912 before the execution of the address 0002H in order to realize the branch processing by this method.
It is necessary to write “0100H”, which is the post-branch address, to 11 by a dedicated instruction. That is, the user must code two dedicated instructions before process two. Similarly, for the branch instructions at addresses 0102H and 0202H, it is necessary to code two dedicated instructions for one branch process.

FIG. 1 shows an example of a program with these changes.
It is shown in FIG. In FIG. 12, the addresses stored in processing 1 to processing 4 are different because a dedicated instruction is added to the program in FIG. In FIG. 12, instruction fetch, instruction decoding, and execution are started from address 0000H after power-on. The before-branch address table 9 at address 0000H is written in
12 is written with 0001H, which is the storage address of process 2, and the branch destination address table 911 is written with 0100H, which is the branch destination, in the post-branch address table 911 at address 0001H. Thereafter, processing 1 and processing 2
The value of the program counter 9 at the time of the fetch is compared with the value on the pre-branch address table 912 by the address comparator 906. When fetching 0003H storing the processing 2, the address comparator 9
06 outputs an address match signal and is input to the selector 8. The post-branch address table receives position information of the matching data of the pre-branch address table, selects corresponding address data on the post-branch address table 911 based on the position information, and supplies the selected address data to the selector 8. The selector 8 selects “0100H”, which is the address data from the post-branch address table 911, based on the address match signal from the address comparator 906, and supplies it to the program counter 9. Therefore, after fetching 0003H, 010
Fetch is performed from 0H, and a branch operation is realized. Thereafter, similarly, writing to the pre-branch address table 912 and the post-branch address table 911 is performed to perform the branch operation.

Next, a next address method will be described as a conventional example with reference to FIG. FIG. 13 shows a memory section 121 composed of an instruction section 123 and a next address section 122 selected by a program counter section 124 composed of the program counter 9, an instruction buffer 2 to which the output of the instruction section 123 is connected, and an instruction buffer section. 2 comprises a decoder / execution unit 3 to which the two outputs are connected. Also,
The output of the next address section 122 is input to the program counter 9.

Next address section 122 and instruction section 123
Are assigned to the same address, and the next time the instruction is fetched into the instruction buffer 2, the next address 1
22 is transferred to the program counter 9. That is, in the next address method, a branch address is added to all instructions, and the branch address is fetched at the same time as the instruction fetch, so that there is no fetch time for the branch instruction.

[0010]

The first problem is that in the prior art 1, the number of addresses that can be registered in the pre-branch address table 912 and the post-branch address table 911 is limited. Therefore, in a relatively large-scale program, it is necessary to frequently rewrite the pre-branch address table 912 and the post-branch address table 911, and the performance is reduced. The reason is that the address comparator 90
This is because it is necessary to compare the address value of the program counter 9 with a plurality of pieces of address data on the pre-branch address table 912 according to No. 6. Since the comparison operation is performed between one system clock and several system clocks for each fetch operation, the number of address data that can be compared is limited.

The second problem is that in the first conventional example, the fetch and rewrite time of the table rewrite instruction is newly generated instead of the fetch time of the branch instruction, and the performance is deteriorated. The reason is that if the address data of the pre-branch address table 912 matches the address value of the program counter 9, the post-branch address table 91
This is because it is necessary to perform a series of operations of selecting and reading the address data corresponding to the pre-branch address table 912 on 1 and writing the data to the program counter 9 via the selector 8, which requires a predetermined operation time. .

Another problem with the next address method is that a circuit area increases due to an increase in memory capacity.
This means that the production cost will increase significantly. The reason is that the branch address is stored in every instruction step,
For example, in the case of a computer system having a 64K memory space, a memory element of 16 bits × 64K = 1 Mbit is required. In addition, the branch address must be stored even in an instruction step that does not require a branch. Considering that most steps in a normal program do not require a branch, most of the increased 1 Mbit is used. It is useless.

[0013]

A branch control circuit according to the present invention comprises a pre-branch address buffer for comparing with a program counter, a branch address buffer for transferring to the program counter at the time of branch, a next pre-branch address buffer and a post-branch address. An address of the branch information table data to be supplied to the buffer is provided on the branch information table.

More specifically, a branch information table (FIG. 1)
14), the pre-branch address (FIG. 2), the post-branch address (FIG. 2), and the next table address (FIG. 2) which is the address of the branch information table to be selected next.
The selected data is stored in the pre-branch address buffer (FIG. 1).
12), a branch information control circuit (13 in FIG. 1) to be stored in the post-branch address buffer (11 in FIG. 1), a program counter (9 in FIG. 1), and an address buffer before branch (FIG. 1).
12), and an address comparator (11 in FIG. 1) after branching when a match occurs.
Is selected and stored in the program counter (9 in FIG. 1).

The branch control circuit of the present invention having the above-described configuration has a branch information table having addresses of branch information table data to be supplied to the pre-branch address buffer and the post-branch address buffer. The address data to be compared can be uniquely determined, and this is stored in the pre-branch address buffer and compared with the program counter. Similarly, address data at the time of branching can be uniquely determined, and this is stored in an address buffer after branching, and transferred to a program counter at the time of branching. For this reason, the comparison operation with the program counter and the transfer processing to the program counter at the time of branching are reduced, and high-speed operation is enabled.

[0016]

Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an example of a computer system including a program control circuit and a program counter unit according to the first embodiment of the present invention, and FIG. 2 is a schematic diagram showing a configuration example of a branch information table in FIG. is there. The data of the table in FIG. 2 is an example in which branch information is extracted from the program example in FIG. 11 and a branch information table is configured.

The computer system shown in FIG. 1 includes a memory 1, an instruction buffer 2, a decoder / execution unit 3, a program counter unit 4, and a branch information table unit 5. Are sequentially read and executed. Various processing instructions are stored in the memory 1. The instruction stored in the address specified by the address data output from the program counter unit 4 is read out and supplied to the instruction buffer 2. The instruction buffer 2 fetches an instruction output from the memory 1 and supplies it to the decoder / execution unit 3. The decoder / execution unit 3 fetches an instruction from the instruction buffer 2, decodes the instruction, and executes the processing. The branch information table 5 includes a branch information table 14 in which data is stored in advance by an assembling process or a compiling process before execution of a program, a branch information control circuit 13,
It comprises an address buffer 12 before branching, an address buffer 11 after branching, and an address comparator 6. The branch information table 14 includes a pre-branch address table 141, a post-branch address table 142, and a next table address 143 addressed by a branch information table address.
It consists of.

The branch information control circuit 13 compares the next table address data output from the branch information table 14 with the address match signal 1 supplied from the address comparator 6.
5 is held in a table address 131 which is a holding circuit using a latch clock, the data of the branch information table 14 is selected, and the read pre-branch address data and the read post-branch address data are respectively stored in the pre-branch address buffer 1.
2 and stored in the address buffer 11 after branching. The table address 131 is “000” by a system reset signal.
The address comparator 6 compares the address data output from the program counter unit 4 with the address data stored in the pre-branch address buffer 12. The address output from the program counter unit 4 is initialized. When the data and the address data stored in the pre-branch address buffer 12 match, the address comparator 6 generates an address match signal 15 and supplies it to the program counter unit 4 and the branch information control circuit 1
Supply 3 The branch information control circuit 13 latches the address supplied from the next table address 143 to the table address 131. The program counter unit 4 includes a program counter 9, an incrementer 7, and a selector 8. The address data stored in the program counter 9 is input to the incrementer 7, where the next address data is generated and input to the selector 8. When the address match signal 15 is not supplied from the branch information table 5, the selector 8 selects the output data of the incrementer 7 and supplies it to the program counter 9. When the address match signal 15 is supplied from the branch information table section 5, the selector 8 selects the output data of the post-branch address buffer 11 and supplies this to the program counter 9. The program counter 9 stores the address data supplied from the selector 8 and supplies the address data to the memory 1.

Next, the program counter section 4 will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing a configuration example of the program counter unit 4. It comprises a program counter 9 using a reference clock as a latch clock, a selector 8 and an incrementer 7.

The incrementer 7 comprises a latch circuit 71 using an inverter 73 to which a reference clock is input as a latch clock, and an increment circuit 72. The value of the program counter 9 is input to the increment circuit 72, and the increment circuit 72 always performs an operation of adding "1" to the input value. That is, when the value held by the program counter 9 is “0001H”, the increment circuit 72 adds “1” and “0002”
H. The increment circuit 72 generates “1”.
The added value is input to the latch circuit 71 and held at the falling edge of the reference clock. In the selector 8, the address match signal 15 of the output value from the address comparator 6 is connected to the inverter 83 and the bus switch 82, and the output of the inverter 83 is connected to the bus switch 81. A latch circuit 71 and a post-branch address buffer 11 are connected to the bus switch 81 and the bus switch 82 as bus outputs, respectively.
The output is input to a latch circuit 84 using the inverter 73 as a latch clock. Now, address match signal 1
When the signal No. 5 is not generated, the bus switch 82 is in the “OFF” state, the inverter 83 is “1”, the bus switch 81 is “ON”, and the latch circuit 84
A value of 1 is input and latched by the latch circuit 84 at the falling timing of the reference clock. When the address match signal 15 is generated, the bus switch 81 is turned off because the inverter 83 is set to “0”, the bus switch 82 is turned “on”, and the latch circuit 84 The value is input to the address buffer 11 and is latched by the latch circuit 84 at the falling timing of the reference clock.

When the address match signal 15 is not supplied from the branch information table 5, the value of the address data executing the instruction is incremented at a predetermined timing, and the instructions stored in the memory 1 are sequentially output. . When the address match signal 15 is supplied from the branch information table 5, the post-branch address data output from the post-branch address buffer 11 is fetched, and the instruction of the branch destination stored in the memory 1 is output. The pre-branch address buffer 12 and the post-branch address buffer 11 are updated on the basis of the table address 131 held by 14.

Next, the operation of the first embodiment will be described with reference to a schematic diagram showing a program example of FIG. 4 and a timing chart showing a branch operation of FIG. FIG. 4 shows FIG.
1 is a program example in which the program of FIG. 12 is applied to the first embodiment. Stages A to H in FIG. 5 are added for explanation, and do not show the circuit operation of the first embodiment.

The programmer creates a source program including a branch instruction as described in the instruction column of FIG. This means that it is completely compatible at the source level with a computer system program having ordinary branch instructions. Next, before executing the program, FIG.
4 is divided into the branch information of FIG. 2 and the program of FIG. 4 by assembling or compiling processing, and the branch information of FIG. 2 is stored in the branch information table 14 and the program of FIG.

In FIG. 5, after the power is turned on, the system reset is active, and in stage A, the program counter 9 is initialized to the address 0000H. At stage B, the address data 00
00H is supplied to the memory 1, the instruction is read from the memory 1, fetched by the instruction buffer 2, and executed by the decode / execute unit 3. The address data “0000H” output from the program counter 9 is input to the increment circuit 72 during the reset period, and “1” is added by the increment circuit 72 to “0001”.
H "is generated and latched by the latch circuit 71 at the reset period and at the fall of the reference clock of the stage B. At this time, since the address match signal 15 is not generated, the latch of the selector 8 is latched at the fall of the reference clock. Latched by the circuit 84 and supplied to the incrementer 7,
At stage C, the incremented address data is written back to the program counter 9. Processing 1 and processing 2 are fetched and executed by the above series of operations.

On the other hand, after the power is turned on, in the stage A, the branch information control circuit 13 selects "00" of the branch information table address as an initial state. "00" of the address before branch
01H ”is read out and stored in the address buffer 1 before branching.
2 and the pre-branch address buffer 12 stores it. Similarly, the post-branch address “0100H” is read and supplied to the post-branch address buffer 11, and the post-branch address buffer 11 stores this. Next, in the stage B, the next table address data “01H”
Is read and held.

When the program counter section 4 advances to "0001H" at stage C and fetches the processing 2, the address comparator 6 sets the address data output from the program counter section 4 and the address buffer 12 before branch.
And generates an address match signal 15, which is supplied to the selector 8. The selector 8 selects “0100H”, which is the post-branch address data output from the post-branch address buffer 11 at the falling timing of the reference clock of the stage C in response to the input of the address match signal 15, and the program counter 9 To supply. The address after the branch is supplied to the memory 1 at the timing of the stage D. The address data “0001H” output from the program counter 9 in stage C is input to the increment circuit 72 and
Is added to generate “0002H”, which is latched by the latch circuit 71 at the fall of the reference clock of the stage C. However, at this time, the address match signal 15
Has occurred, the selector 8 supplies the value of the post-branch address buffer 11 “0” at the falling of the reference clock.
100H "is input and latched by the latch circuit 84, the address data of the address buffer 11 is latched after branching to the program counter 9 at stage D. Therefore, after fetching 0001H at stage C, fetching from 0100H at stage D is performed. Performed to implement a branching operation.

On the other hand, in the stage C, the address match signal 15 is supplied from the address comparator 6 to the branch information control circuit 13, and based on the data of the table address 131 held in the branch information control circuit 13, the branch information table 14 Address 01H is selected and “0101H” of the address before branching is selected.
And supplies it to the pre-branch address buffer 12, and the pre-branch address buffer 12 stores this in stage D. Similarly, “0200H” of the post-branch address is read and supplied to the post-branch address buffer 11.
After branching at stage D, the address buffer 11 stores this. In the stage D, the next table address data "02H" is read and held.

Thereafter, similarly, the address comparator 6 compares the address data output from the program counter unit 4 with the address data in the pre-branch address buffer 12, and when they do not match, increments the address data of the program counter 9 to increase the memory. 1 and sequentially executes the instruction processing. When they match, the address comparator 6 supplies the address data of the post-branch address buffer 11 to the program counter 9, supplies the post-branch address to the memory 1, fetches the instruction processing of the branch destination, and performs the branch operation.

As described above, in the first embodiment, a next table address is provided, and the next branch address data and the post-branch address data to be next branched are uniquely selected according to the next table address, and each is selected as the pre-branch address. Buffer 12 and post-branch address buffer 1
By storing the address data in 1, the operation of supplying the address data after branching to the program counter 9 when the comparison operation and the coincidence by the address comparator 6 coincide with each other can be speeded up. Also, since address data is stored in the branch information table 14 in advance, a dedicated instruction for writing to the branch information table 14 is unnecessary, and complete compatibility at the source level with a program using a normal branch instruction is provided. Yes, no program modification is required. Also, the object code stored in the memory 1 can be applied to the present invention by setting the instruction storage address immediately before the branch instruction as the pre-branch address of the branch information table, so that the object code level is compatible. Further, the circuit is simple, and the amount of hardware is much smaller than that of other high-speed computer systems such as the next address method and pipeline control.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 6 is a block diagram showing an example of a computer system having a program control circuit according to the second embodiment of the present invention, FIG. 7 is a schematic diagram showing an example of a program executed in FIG. 6, and FIG. 9 is a schematic diagram illustrating a configuration example of a branch information table of FIG. 8, in which data in the table of FIG. 8 is obtained by extracting branch information from a source program of the program of FIG. 7 and forming a branch information table.

The computer system shown in FIG. 6 includes a memory 1, an instruction buffer 2, and a decoder / execution unit 3.
, A program counter unit 504, and a branch information table 505. Since the functions having the same numbers as those in the first embodiment perform the same operations, the description will be omitted. The program counter unit 504 is the same as the first embodiment except that the selector 508 has a function of selecting three inputs.

The branch information table unit 505 includes a branch information table 514 in which data is stored in advance by an assembling process or a compiling process before execution of the program.
Branch information control circuit 513 and pre-branch address buffer 1
2, a post-branch address buffer 11, a pre-branch address table 520, a branch condition table 521, a post-branch address table 522, a branch next table address 523, and a non-branch next table address 5.
24.

The branch information control circuit 513 is output from the branch next table address 523 and the non-branch next table address 524 of the branch information table 514 based on the branch condition match signal 515 supplied from the branch condition determination circuit 516. A table address selector 519 for selecting the next table address data, and a table address 518 as a holding circuit using the next table address data output from the table address selector 519 as an address match signal 15 supplied from the address comparator 6 as a latch clock. Consists of The output address from the table address 518 is supplied to each address table of the branch information table 514.

As shown in FIG. 8, the branch condition table 521 has positive and negative condition values of Z flags of Z = 0 and Z = 1. That is, when the branch condition is “Z = 1”, the value of the column of Z = 0 is “1” and the value of the column of Z = 1 is “1” as shown in the branch condition table address 0 in FIG. ". When the branch condition is “Z = 0”, the value of the column of Z = 0 is “1” as shown in the branch condition table address 10 in FIG.
The value in the column of Z = 1 is “0”. When the branch condition is “none”, that is, “Z = 0 or Z = 1”, as shown in the branch condition table address 11 in FIG. 8, the value of the column of Z = 0 is set to “1”, and Z = 1 Is also "1".

The branch condition determination circuit 516 has a positive condition value of the Z flag supplied from the branch condition table 521, the Z flag output from the decoder / execution unit 3, and the address coincidence signal 15 supplied from the address comparator 6. Is input to the OR circuit via the first AND circuit. Further, the negative condition value of the Z flag supplied from the branch condition table 521, the inverted value of the value of the Z flag output from the decoder / execution unit 3, and the address match signal 15 supplied from the address comparator 6 are the second values. , And this output is the other input of the OR circuit. That is, the logical product of the positive condition value of the Z flag supplied from the branch condition table 521, the value of the Z flag output from the decoder / execution unit 3, and the address match signal 15, and the Z supplied from the branch condition table 521 The logical OR of the negative condition value of the flag, the inverted value of the value of the Z flag output from the decoder / execution unit 3 and the address match signal 15 is calculated, and the result is output as a condition match signal.

The pre-branch address data read from the branch information table 514, the branch condition, and the post-branch address data are stored in the pre-branch address buffer 12, the branch condition buffer 517, and the post-branch address buffer 11, respectively.
To be stored. The address comparator 6 compares the address data output from the program counter unit 504 with the address data stored in the pre-branch address buffer 12. When the address data output from the program counter unit 4 matches the address data stored in the pre-branch address buffer 12, the address comparator 6 generates an address match signal 15 and sends it to the branch condition determination circuit 516. Supply. The branch condition determination circuit 516 is supplied with the Z flag of the execution result from the decoder / execution unit 3 and the branch condition value of the Z flag from the branch condition buffer 517.

Therefore, when the address match signal 15 from the address comparator 6 matches the value of the Z flag from the decoder / execution unit 3 with the branch condition value of the Z flag in the branch condition buffer 517, the branch condition determination circuit 516 Output a branch condition match signal 515. Branch condition judgment circuit 5
The output of 16 is supplied to the selector 8 and the branch information control circuit 513. When the address match signal 15 of the address comparator 6 is also supplied to the branch information control circuit 513, the address match signal 15 of the address comparator 6 is generated and when the address match signal 15 is supplied from the branch condition determination circuit 516. The address data of the next address table 523 at the time of branching is read, and an address match signal 15 is generated from the address comparator 6, and the branch condition determination circuit 51
When “0” is supplied from 6, the address data of the next address table 524 at the time of non-branch is read. The branch information control circuit 513 selects the read next table address data by the table address selector 519, and holds the selected next table address data in the table address 518.

Next, the operation of the second embodiment will be described with reference to a schematic diagram showing an example of a program in FIG. 7 and a timing chart showing a branch operation in FIG. The stages a to h in FIG. 8 are added for explanation, and do not show the circuit operation of the second embodiment.

In the program of FIG. 7, JUMP Z
= 1, nnnnH is nn when the zero flag is set to "1" by the execution result of the instruction in the decoder / execution unit 3.
Branching to nnH, JUMP Z = 0, nnnnH indicates that branching to nnnnH is performed when the zero flag becomes “0” according to the execution result of the instruction in the decoder / execution unit 3. As in the first embodiment, the branch information in FIG. 7 is stored in the branch information table 514, and the processing of the program is stored in the memory 1.

In FIG. 6, after the power is turned on, the program counter 9 is initialized to the address 0000H, and the address data 000 is transmitted from the program counter unit 4 at a predetermined timing.
0H is supplied to the memory 1, an instruction is read from the memory 1, fetched by the instruction buffer 2, and
It is executed by the execution unit 3. The address data output from the program counter 9 is stored in the incrementer 7
And the address data of the program counter 9 is incremented. Processing 1 by the above series of operations
Fetch and execute process 2.

On the other hand, after the power is turned on, in stage a, the branch information control circuit 513 selects “0” of the branch information table address as an initial state and “0001” of the pre-branch address.
H "is read out and supplied to the pre-branch address buffer 12. The pre-branch address buffer 12 stores the same.
H "is read and supplied to the post-branch address buffer 11. The post-branch address buffer 11 stores the read H. The branch condition" 1 "is read, supplied to the branch condition buffer 517, and stored. The next table address data “10” at the time of branching and the next table address data “1” at the time of non-branching are read out and input to the table address selector 519.

When the program counter section 4 advances to "0001H" at stage c and fetches the processing 2, the address comparator 6 determines whether the address data output from the program counter section 504 and the address data in the pre-branch address buffer 12 are present. And an address match signal 15
And supplies it to the branch condition determination circuit 516.

Now, the stage c in the execution result of the process 2
It is assumed that the zero flag becomes "1" at the fall of the reference clock. At this time, Z = “1” is stored as the branch condition in the branch condition buffer 517, and the branch condition matches. At this time, a branch condition matching signal 515 is output from the branch condition determination circuit 516 at the fall of the reference clock of the stage c, and the selector 8 and the branch information control circuit 513 are output.
Supplied to At the same time, the selector 8 selects “0100H”, which is the post-branch address data output from the post-branch address buffer 11 in response to the supply of the branch condition match signal 515 from the branch condition determination circuit 516, and sends it to the program counter 9. Supply. At stage d, the program counter 9 sets the address data "0100" after branching.
Accordingly, after fetching 0001H at stage c, fetch is performed from 0100H at stage d, thereby implementing a branch operation.

On the other hand, at stage c, the branch condition match signal 51
5 is supplied to the table address selector 519, the next table address data at the time of branch is selected, the address match signal 15 is input, and the next table address data "10H" at the time of branch is stored in the table address 518. At stage d, the address “10H” is supplied from the table address 518 to the branch information table 514, “0101H” is stored in the pre-branch address buffer 12, and “0200H” is stored in the post-branch address buffer 11.
Is stored, and “Z = 0” is stored in the branch condition buffer 517.

Next, at stage e, when the program counter section 4 advances to "0101H" and fetches the processing 5, the address comparator 6 makes the address data output from the program counter section 504 and the address of the pre-branch address buffer 12 The data is compared and the address match signal 15
And supplies it to the branch condition determination circuit 516.

When the reference clock of the stage e falls, the Z flag is set to "1" in the execution result of the processing 5.
Let's say At this time, “Z = 0” is stored as the branch condition in the branch condition buffer 517, and the branch condition does not match. At this time, the branch condition determination signal 515 is not output from the branch condition determination circuit 516. Selector 8
Is a branch condition match signal 515 from the branch condition determination circuit 516.
Is not supplied, the incrementer 7 is selected and supplied to the program counter 9. Therefore, 010
After fetching 1H, fetch is performed from 0102H, and the branch operation is not performed.

On the other hand, at stage e, the branch condition match signal 51
5 is not supplied to the table address selector 519, the non-branch next table address data is selected, the address match signal 15 is input, and the non-branch next table address data “11H” is stored in the table address 518. At stage f, the address “11H” is supplied from the table address 518 to the branch information table 514, and “0” is supplied to the pre-branch address buffer 12.
102H "is stored," 0200H "is stored in the post-branch address buffer 11, and" Z = 0 or Z = 1 "is stored in the branch condition buffer 517.

Thereafter, similarly, the address comparator 6 compares the address data output from the program counter unit 4 with the address data in the pre-branch address buffer 12 and the branch condition. Are incremented and supplied to the memory 1 to sequentially execute the instruction processing. When the branch condition is met, the address data in the post-branch address buffer 11 is supplied to the program counter 9, the post-branch address is supplied to the memory 1, the instruction processing of the branch destination is fetched, and the branch operation is performed.

As described above, in the second embodiment, the next table address at the time of branch and the next table address at the time of non-branch are provided, and the address data before branch and the address after branch regardless of the presence or absence of the branch operation. By uniquely selecting data and storing them in the pre-branch address buffer 12 and the post-branch address buffer 11, respectively, the comparison operation by the address comparator 6 and the supply of the post-branch address data to the program counter 9 when they match. The operation can be speeded up. Also, the branch information table 51
No. 4 stores address data in advance, so that a write-only instruction to the branch information table 514 is unnecessary.
It is completely compatible at the source level with a program using a normal branch instruction, and no program modification is required. Also, the object code stored in the memory 1 can be applied to the present invention by setting the instruction storage address immediately before the branch instruction as the pre-branch address of the branch information table, so that the object code level is compatible.

In the second embodiment, only the Z flag is used as the branch condition. However, it is apparent that the branch conditions such as the carry flag and the sign flag can be increased by increasing the branch condition buffer. . Similarly,
It is clear that multidirectional branching can be easily realized by increasing the number of branch condition buffers and the number of address buffers after branching.

[0052]

The first effect is that there is no restriction on the number of addresses that can be registered as the pre-branch address and the post-branch address in the branch information table. For this reason, even before a large-scale program, all the pre-branch addresses and the post-branch addresses can be registered in the branch information table, so that the performance does not deteriorate due to the large-scale program. The reason is that by providing the branch information table address to be selected next on the branch information table, the pre-branch address and the post-branch address to be compared with the program counter can be uniquely determined. This is for storing in a buffer.

The second effect is that the fetch time and the rewrite time of the rewrite instruction of the branch information table do not occur at all, so that the performance is greatly improved. The reason is,
Since there is no restriction on the number of addresses that can be registered in the pre-branch address and the post-branch address of the branch information table, it is possible to prepare branch information in the branch information table in advance, and there is no need to rewrite the branch information table. This is because

A third effect is that it is compatible with a program using a normal branch instruction. For this reason, when a huge program in the past is used in the present invention, the program does not need to be modified, and the number of steps can be significantly reduced. The reason is that it is possible to prepare the branch information in the branch information table in advance, and it is not necessary to rewrite the branch information table. Therefore, the data to be stored in the branch information table in the assembling process or the compile process is not required. Can be generated.

A fourth effect is that performance is greatly improved because no operation time is required for the branch operation. Specifically, when 1-byte data transfer processing requiring 10 branch operations is compared with the case of using a normal branch instruction, the processing time is reduced by 24.7%, and
In the case of the data transfer processing of 0 bytes, the processing time of 41.0% is reduced. The reason is that when the address data of the address buffer before branching matches the address value of the program counter, the address data of the address buffer after branching is written to the program counter 9, so that the normal incrementer writes back to the program counter. This is because they can be performed at exactly the same timing.

A fifth advantage is that the amount of hardware is much smaller than that of other high-speed computer systems, for example, the next address method or pipeline control, and the increase in manufacturing cost can be suppressed. It is. The reason is that the control circuit for performing the branch processing is simple, and the pre-branch address and the post-branch address in the branch information table are only the address data requiring the branch processing, so that there is no waste.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a computer system including a program control circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating a configuration example of a branch information table according to the first embodiment;

FIG. 3 is a block diagram illustrating a program counter unit of a computer system having an embodiment of the present invention.

FIG. 4 is a schematic diagram showing a program example for explaining the first embodiment;

FIG. 5 is a timing chart showing a branch operation of the first embodiment.

FIG. 6 is a block diagram showing an example of a computer system including a second embodiment of the program control circuit according to the present invention.

FIG. 7 is a schematic diagram showing an example of a program for explaining a second embodiment.

FIG. 8 is a schematic diagram illustrating a configuration example of a branch information table according to the second embodiment;

FIG. 9 is a timing chart showing a branch operation according to the second embodiment.

FIG. 10 is a block diagram illustrating an example of a computer system including a conventional branch control circuit.

FIG. 11 is a schematic diagram showing an example of a program using a branch instruction for explaining a conventional example.

FIG. 12 is a schematic diagram showing a program in which a branch instruction for describing a conventional example is rewritten with a dedicated instruction.

FIG. 13 is a block diagram showing an example of a computer system provided with another conventional branch control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory 2 instruction buffer 3 decoder / execution unit 4 program counter part 5 branch information table part 6 address comparator 7 incrementer 8 selector 9 program counter 11 post-branch address buffer 12 pre-branch address buffer 13 branch information control circuit 14 branch information table 15 Address match signal 513 Branch information control circuit 514 Branch information table 515 Branch condition match signal 516 Branch condition judgment circuit 517 Branch condition buffer 911 Address after branch address 912 Address table before branch 906 Address comparator 121 Memory unit 122 Next address unit 123 Instruction Section 124 Program counter section

Claims (3)

(57) [Claims] When a branch is made in the middle of an instruction, a plurality of pieces of branch information data are set as data consisting of address data before branch, address data after branch, and branch information table address data as a set of branch information data. And a branch information table for storing a set of the branch information table, and a branch for designating a set of branch information data on the branch information table and transferring the set to a pre-branch address buffer, a post-branch address buffer, and a branch information table address pointer. An information control circuit;
An address comparator that compares the value of a program counter with the pre-branch address data value held in the pre-branch address buffer, and activates and outputs an address match signal when these data values match. And when the address match signal is inactive, the program
Selecting the data obtained by incrementing the value of the counter, and selecting the post-branch address data held in the post-branch address buffer and transferring it to the program counter when the address match signal is active; A program counter unit for designating an address of a memory in which an instruction to be executed is stored. 2. A set of branch information data in a branch information table portion includes: pre-branch address data; branch condition data;
Address after branch when the branch condition data is satisfied
Data, address data of a memory storing an instruction to be executed next when the branch condition is not satisfied, and address data of a branch information table to be referred next when the branch condition is satisfied The branch information control circuit designates a set of branch information data on the branch information table according to the coincidence / mismatch of the branch condition, and the branch information data designated by the branch information control circuit. Is compared with the branch condition flag data output from the processing instruction, and when these branch condition data match, the address match signal is activated, and when the branch condition data does not match, 2. The branch control circuit according to claim 1, further comprising a branch condition determination circuit for making it inactive. 3. The branch information data of the branch information table section is generated beforehand by a branch information data generating means before execution of a program.
2. The branch control circuit according to 1.