JPH0426494B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a string data control circuit in a microprocessor, and more particularly to a string data control circuit for processing byte string data that is not a word boundary.

(Prior Art) In a data processing device, when processing byte string data stored in an external storage device that can be accessed in units of words consisting of multiple bytes, processing is performed in units of words using a microprocessor. Even if the data is read for the purpose of executing the data, if the data is not specified by the word boundary, the byte positions of the two word data read in one hour may be shifted, so the data digits must be aligned. It was impossible. However, since controlling data digit alignment is complicated, conventionally data has generally had to be accessed and processed in byte units.

(Problems to be Solved by the Invention) As explained above, according to the prior art, data access and operations are performed sequentially one byte at a time, so many steps need to be executed, especially when the data is long. The disadvantage was that the processing speed was slow.

The purpose of the present invention is to perform a byte-by-byte shift in a word width consisting of multiple bytes, store a lower part of the address of two byte string data, and then use the stored information to perform a byte-by-byte shift. This problem can be solved by determining the word-width byte string data, temporarily storing the byte string data in word width, and then merging it according to the byte ring shift function, so that operations can be performed in word width. An object of the present invention is to provide a sling data control circuit configured as follows.

(Means for Solving the Problems) A string data control circuit according to the present invention includes a byte ring shifter, a pair of address registers,
It is configured to include a function determining block, first to third data registers, and an arithmetic block.

A byte ring shifter is used to perform byte-by-byte shifts in a word width consisting of multiple bytes.

The pair of address registers are for storing part of the lower addresses of the pair of byte string data.

The function determination block is for determining the function of the byte ring shifter from the information stored in the pair of address registers.

The first data register has a size equal to the word width and is for temporarily storing byte string data.

The second data register shifts the contents of the first data register with the byte ring shifter, and then
It is used to temporarily store the results.

The third data register contains the result obtained by shifting the contents of the first data register by the byte ring shifter and the data obtained by merging the contents of the second data register according to the function of the byte ring shifter. It is for storing.

The arithmetic block is for word-width arithmetic on the contents of the first and third data registers.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a string data control circuit according to the present invention. In FIG. 1, 1 is a microprocessor to which the present invention is applied, 2 is an external storage device for storing byte string data, and 3 to 5 are 4-byte wide storage devices for temporarily storing byte string data. 1 to 3rd data registers, 6 a byte ring shifter, 7 a function block for determining the function of the byte ring shifter 6;
8 and 9 are address registers for storing the lowest two bits of each address of two byte string data, 10 is an address generation block for generating the address of the byte string data, and 11 is a 4-byte wide arithmetic block. , 20 is a 4-byte wide data bus from the external storage device 2,
21 is an address for giving the address generated by the address generation block 10 to the external storage device 2.

FIG. 2 is an explanatory diagram showing two byte string data used in this embodiment. The data shown in FIG. 2 is stored in the external storage device 2,
AS1 represents the address of data A, AS2 represents the address of data B, and the least significant two bits of each are
11, 01, A1 to A3 and B1 to B3 are 4-byte boundary (4-byte width) data units that are accessed at one time.

FIG. 3 is an explanatory diagram showing the types of functions of the byte ring shifter 6, their operations, and how to determine the functions by a combination of two data stored in the registers 8 and 9. .

FIG. 4 is an explanatory diagram showing the process of processing the data in FIG. 2 in this embodiment. Next, the fourth
The operation of this embodiment will be explained according to the figures. In FIG. 4, in the phase, the first data register 3
The lowest two bits of AS1 and AS2 stored in
11,01, the function of the bite ring shifter 6 is set to the 2-byte exchange mode according to FIG. 3 by the function determining block 7, and the bite ring shifter 6 is operated as a shifter that performs a 2-byte exchange. Thereafter, the first 4 bytes of data A1 of data A are stored in the first data register 3, and the contents are further stored in the second data register 4 through the byte ring shifter 6.

Next, in the phase, after storing the next 4 bytes of data A2 in the register 3, its contents are combined with the data obtained through the byte ring shifter 6 and the data stored in the second data register 4 in the phase. are merged and stored in the third data register 5. This merging method also follows the function determined by the function determination block. Thereafter, the output data of the bite ring shifter 6 is stored in the second data register 4.
Since the third data register 5 stores data A whose digits are aligned with data B, when the first 4 bytes of data B1 of data B are subsequently read into the first data register 3 in the phase, the calculation is performed. Calculation can be performed directly in block 11.

Similarly, the next 4 bytes of data A3 after data A are read in the phase, merged with the data previously stored in the second data register 4, stored in the third data register 5, and stored in the third data register 5. New contents are set in the data register 4 of No. 2. Next, when the next 4 bytes of data B1 after data B are read in the phase, the second operation data is set in the first data register 3 and the third data register 5, and the second operation data is set in the operation block 11. Perform calculations. In the final episode, the last one remaining in the second data register 4 is
After transferring the byte d ₁ ' to the third data register 5, the last 4 bytes of data B3 of data B can be read into the first data register 3 in the phase, and the final calculation can be performed in the calculation block 11. .

In this embodiment, one word consists of 4 bytes, but the present invention is not limited to 4 bytes, and one word consists of 2 bytes, or even 8 bytes.
Even if it consists of bytes, digit alignment and operations can be performed in the same way.

(Effects of the Invention) As explained above, in the present invention, by operating the byte ring shifter using the information of the lower bits of the data address, data digit alignment can be easily performed even for data that is not a word boundary. This has the advantage that word-width operations can be easily executed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a string data control circuit according to the present invention. FIG. 2 is an explanatory diagram showing the status of two byte string data in this embodiment. FIG. 3 is an explanatory diagram showing the types of functions of the bite ring shifter, their operations, and conditions for determining the functions. FIG. 4 is an explanatory diagram showing the operation process of this embodiment.

1...Microprocessor, 2...External storage device, 3-5, 8-9...Register, 6...Byte ring shifter, 7...Shift function determination block, 10...Data address generation block, 11 ...Arithmetic block, 20, 21...Bus, AS1, AS2...Address, A1 to A3, B
1-B3...Data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a string data control circuit according to the present invention. FIG. 2 is an explanatory diagram showing the status of two byte string data in this embodiment. FIG. 3 is an explanatory diagram showing the types of functions of the bite ring shifter, their operations, and conditions for determining the functions. FIG. 4 is an explanatory diagram showing the operation process of this embodiment. pay. This merging method also follows the function determined by the function determination block.
Thereafter, the output data of the bite ring shifter 6 is stored in the second data register 4. Since the third data register 5 stores data A whose digits are aligned with data B, the first 4 of data B are then stored in the first data register 3 in the phase.
When byte data B1 is read, calculation block 1
1 allows you to perform calculations as is. Similarly, the next 4 bytes of data A3 after data A are read in the phase, merged with the data previously stored in the second data register 4, stored in the third data register 5, and stored in the third data register 5. New contents are set in the data register 4 of No. 2. Next, when the next 4 bytes of data B1 after data B are read in the phase, the second operation data is set in the first data register 3 and the third data register 5, and the second operation data is set in the operation block 11. Perform calculations. In the final episode, the last one remaining in the second data register 4 is
After transferring the byte d ₁ ' to the third data register 5, the last 4 bytes of data B3 of data B can be read into the first data register 3 in the phase, and the final calculation can be performed in the calculation block 11. . In this embodiment, one word consists of 4 bytes, but the present invention is not limited to 4 bytes, and one word consists of 2 bytes, or even 8 bytes.
Even if it consists of bytes, digit alignment and operations can be performed in the same way. (Effects of the Invention) As explained above, in the present invention, by operating the byte ring shifter using the information of the lower bits of the data address, data digit alignment can be easily performed even for data that is not a word boundary. This has the advantage that word-width operations can be easily executed.

Claims (1)

[Claims] 1. A byte ring shifter for performing a byte-by-byte shift in a word width consisting of multiple bytes, a pair of address registers for storing a part of the lower address of a pair of byte string data, and storage in the pair of address registers. a first data register having a size equal to a word width and for temporarily storing the byte string data; a second data register for temporarily storing the contents after shifting the contents of the first data register by the byte ring shifter; and a second data register for temporarily storing the contents after shifting the contents of the first data register by the byte ring shifter; a third data register for storing the result obtained by merging the contents of the second data register and the data obtained by merging the contents of the second data register according to the function of the byte ring shifter; 1. A string data control circuit comprising: a calculation block for calculating contents in word width.